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<meta http-equiv="Content-Type" content="text/html; charset=utf-8">
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- <title>LLVM 1.6 Release Notes</title>
+ <title>LLVM 1.7 Release Notes</title>
</head>
<body>
-<div class="doc_title">LLVM 1.6 Release Notes</div>
+<div class="doc_title">LLVM 1.7 Release Notes</div>
<ol>
<li><a href="#intro">Introduction</a></li>
<div class="doc_text">
<p>This document contains the release notes for the LLVM compiler
-infrastructure, release 1.6. Here we describe the status of LLVM, including any
+infrastructure, release 1.7. Here we describe the status of LLVM, including any
known problems and major improvements from the previous release. The most
up-to-date version of this document can be found on the <a
-href="http://llvm.org/releases/1.6/">LLVM 1.6 web site</a>. If you are
+href="http://llvm.org/releases/">LLVM releases web site</a>. If you are
not reading this on the LLVM web pages, you should probably go there because
this document may be updated after the release.</p>
<div class="doc_text">
-<p>This is the seventh public release of the LLVM Compiler Infrastructure. This
-release incorporates a large number of enhancements and additions (primarily in
-the code generator), which combine to improve the quality of the code generated
-by LLVM by up to 30% in some cases. This release is also the first release to
-have first-class support for Mac OS/X: all of the major bugs have been shaken
-out and it is now as well supported as Linux on X86.</p>
+<p>This is the eighth public release of the LLVM Compiler Infrastructure. This
+release incorporates a large number of enhancements and new features,
+including vector support (Intel SSE and Altivec), a new GCC4.0-based
+C/C++ front-end, Objective C/C++ support, inline assembly support, and many
+other big features.
+</p>
</div>
<!--=========================================================================-->
<div class="doc_subsection">
-<a name="newfeatures">New Features in LLVM 1.6</a>
+<a name="newfeatures">New Features in LLVM 1.7</a>
</div>
<!--_________________________________________________________________________-->
-<div class="doc_subsubsection"><a name="iselgen">Instruction Selector
-Generation from Target Description</a></div>
+<div class="doc_subsubsection"><a name="llvmgcc4">GCC4.0-based llvm-gcc
+front-end</a></div>
<div class="doc_text">
-<p>LLVM now includes support for auto-generating large portions of the
-instruction selectors from target descriptions. This allows us to
-write patterns in the target .td file, instead of writing lots of
-nasty C++ code. Most of the PowerPC instruction selector is now
-generated from the PowerPC target description files and other targets
-are adding support that will be live for LLVM 1.7.</p>
-<p>For example, here are some patterns used by the PowerPC backend. A
-floating-point multiply then subtract instruction (FMSUBS):</p>
+<p>LLVM 1.7 includes a brand new llvm-gcc, based on GCC 4.0.1. This version
+of llvm-gcc solves many serious long-standing problems with llvm-gcc, including
+all of those blocked by the <a href="http://llvm.org/PR498">llvm-gcc 4 meta
+bug</a>. In addition, llvm-gcc4 implements support for many new features,
+including GCC inline assembly, generic vector support, SSE and Altivec
+intrinsics, and several new GCC attributes. Finally, llvm-gcc4 is
+significantly faster than llvm-gcc3, respects -O options, its -c/-S options
+correspond to GCC's (they emit native code), supports Objective C/C++, and
+it has debugging support well underway.</p>
-<div class="doc_code"><p>
-<tt>(set F4RC:$FRT, (fsub (fmul F4RC:$FRA, F4RC:$FRC), F4RC:$FRB))</tt>
-</p></div>
+<p>If you can use it, llvm-gcc4 offers significant new functionality, and we
+hope that it will replace llvm-gcc3 completely in a future release.
+Unfortunately, it does not currently support C++ exception handling at all, and
+it only works on Apple Mac OS/X machines with X86 or PowerPC processors.
+</p>
-<p>Exclusive-or by 16-bit immediate (XORI):</p>
-
-<div class="doc_code"><p>
-<tt>(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))</tt>
-</p></div>
-
-<p>Exclusive-or by 16-bit immediate shifted right 16-bits (XORIS):</p>
+</div>
-<div class="doc_code"><p>
-<tt>(set GPRC:$dst, (xor GPRC:$src1, imm16Shifted:$src2))</tt>
-</p></div>
+<!--_________________________________________________________________________-->
+<div class="doc_subsubsection"><a name="inlineasm">Inline Assembly
+Support</a></div>
-<p>With these definitions, we teach the code generator how to combine these two
-instructions to xor an abitrary 32-bit immediate with the following
-definition. The first line specifies what to match (a xor with an arbitrary
-immediate) the second line specifies what to produce:</p>
+<div class="doc_text">
-<div class="doc_code"><p>
-<pre>def : Pat<(xor GPRC:$in, imm:$imm),
- (XORIS (XORI GPRC:$in, (LO16 imm:$imm)), (HI16 imm:$imm))>;
-</pre>
-</p></div>
+<p>The LLVM IR and llvm-gcc4 front-end now fully support arbitrary GCC <a
+href="LangRef.html#inlineasm">inline assembly</a>. The LLVM X86 and PowerPC
+code generators have initial support for it,
+being able to compile basic statements, but are missing some features. Please
+report any inline asm statements that crash the compiler or that are miscompiled
+as bugs.</p>
</div>
<!--_________________________________________________________________________-->
-<div class="doc_subsubsection"><a name="sched">Instruction Scheduling
-Support</a></div>
+<div class="doc_subsubsection"><a name="newsparc">New SPARC backend</a></div>
<div class="doc_text">
-<p>Instruction selectors using the refined <a
-href="CodeGenerator.html#instselect">instruction selection framework</a> can now
-use a simple pre-pass scheduler included with LLVM 1.6. This scheduler is
-currently simple (cannot be configured much by the targets), but will be
-extended in the future.</p>
+<p>LLVM 1.7 includes a new, fully functional, SPARC backend built in the
+target-independent code generator. This SPARC backend includes support for
+SPARC V8 and SPARC V9 subtargets (controlling whether V9 features can be used),
+and targets the 32-bit SPARC ABI.</p>
+
+<p>The LLVM 1.7 release is the last release that will include the LLVM "SparcV9"
+backend, which was the very first LLVM native code generator. It will
+be removed in LLVM 1.8, being replaced with the new SPARC backend.</p>
+
</div>
<!--_________________________________________________________________________-->
-<div class="doc_subsubsection"><a name="subtarget">Code Generator Subtarget
-Support</a></div>
+<div class="doc_subsubsection"><a name="genvector">Generic Vector Support
+</a></div>
<div class="doc_text">
-<p>It is now straight-forward to parameterize a target implementation, and
-provide a mapping from CPU names to sets of target parameters. LLC now supports
-a <tt>-mcpu=cpu</tt> option that lets you choose a subtarget by CPU name: use
-"<tt>llvm-as < /dev/null | llc -march=XXX -mcpu=help</tt>" to get a list of
-supported CPUs for target "XXX". It also provides a
-<tt>-mattr=+attr1,-attr2</tt> option that can be used to control individual
-features of a target (the previous command will list available features as
-well).</p>
-<p>This functionality is nice when you want tell LLC something like "compile to
-code that is specialized for the PowerPC G5, but doesn't use altivec code. In
-this case, using "<tt>llc -march=ppc32 -mcpu=g5 -mattr=-altivec</tt>".</p>
+<p>LLVM now includes significantly extended support for SIMD vectors in its
+core instruction set. It now includes three new instructions for manipulating
+vectors: <a href="LangRef.html#i_extractelement"><tt>extractelement</tt></a>,
+<a href="LangRef.html#i_insertelement"><tt>insertelement</tt></a>, and
+<a href="LangRef.html#i_shufflevector"><tt>shufflevector</tt></a>. Further,
+many bugs in vector handling have been fixed, and vectors are now supported by
+the target-independent code generator. For example, if a vector operation is
+not supported by a particular target, it will be correctly broken down and
+executed as scalar operations.</p>
+<p>Because llvm-gcc3 does not support GCC generic vectors or vector intrinsics,
+llvm-gcc4 must be used.</p>
</div>
+
<!--_________________________________________________________________________-->
-<div class="doc_subsubsection"><a name="jitlock">Other New Features</a></div>
+<div class="doc_subsubsection"><a name="ssealtivec">Intel SSE and PowerPC
+Altivec support
+</a></div>
<div class="doc_text">
-<ol>
- <li>The JIT now uses mutexes to protect its internal data structures. This
- allows multi-threaded programs to be run from the JIT or interpreter without
- corruption of the internal data structures. See
- <a href="http://llvm.org/PR418">PR418</a> and
- <a href="http://llvm.org/PR540">PR540</a> for the details.
- </li>
- <li>LLVM on Win32 <a href="http://llvm.org/PR614">no longer requires sed,
- flex, or bison when compiling with Visual C++</a>.</li>
- <li>The llvm-test suite can now use the NAG Fortran to C compiler to compile
- SPEC FP programs if available (allowing us to test all of SPEC'95 &
- 2000).</li>
- <li>When bugpoint is grinding away and the user hits ctrl-C, it now
- gracefully stops and gives what it has reduced so far, instead of
- giving up completely. In addition, <a href="http://llvm.org/PR576">the JIT
- debugging mode of bugpoint is much faster</a>.</li>
- <li>LLVM now includes Xcode project files in the llvm/Xcode directory.</li>
- <li>LLVM now supports Mac OS/X on Intel.</li>
- <li>LLVM now builds cleanly with GCC 4.1.</li>
-</ol>
-</div>
-<!--=========================================================================-->
-<div class="doc_subsection">
-<a name="codequality">Code Quality Improvements in LLVM 1.6</a>
+<p>The LLVM X86 backend now supports Intel SSE 1, 2, and 3, and now uses scalar
+SSE operations to implement scalar floating point math when the target supports
+SSE1 (for floats) or SSE2 (for doubles). Vector SSE instructions are generated
+by llvm-gcc4 when the generic vector mechanism or specific SSE intrinsics are
+used.
+</p>
+
+<p>The LLVM PowerPC backend now supports the Altivec instruction set, including
+both GCC -maltivec and -faltivec modes. Altivec instructions are generated
+by llvm-gcc4 when the generic vector mechanism or specific Altivec intrinsics
+are used.
+</p>
+
</div>
+<!--_________________________________________________________________________-->
+<div class="doc_subsubsection"><a name="optimizernew">Optimizer
+Improvements</a></div>
+
<div class="doc_text">
-<ol>
- <li>The <tt>-globalopt</tt> pass can now statically evaluate C++ static
- constructors when they are simple enough. For example, it can
- now statically initialize "<tt>struct X { int a; X() : a(4) {} } g;</tt>".
- </li>
- <li>The Loop Strength Reduction pass has been completely rewritten, is far
- more aggressive, and is turned on by default in the RISC targets. On PPC,
- we find that it often speeds up programs from 10-40% depending on the
- program.</li>
- <li>The code produced when exception handling is enabled is far more
- efficient in some cases, particularly on Mac OS/X.</li>
-</ol>
+<ul>
+<li>The Loop Unswitching pass (<tt>-loop-unswitch</tt>) has had several bugs
+ fixed, has several new features, and is enabled by default in llvmgcc3
+ now.</li>
+<li>The Loop Strength Reduction pass (<tt>-loop-reduce</tt>) is now enabled for
+ the X86 and Alpha backends.</li>
+<li>The Instruction Combining pass (<tt>-instcombine</tt>) now includes a
+ framework and implementation for simplifying code based on whether computed
+ bits are demanded or not.</li>
+<li>The Scalar Replacement of Aggregates pass (<tt>-scalarrepl</tt>) can now
+ promote simple unions to registers.</li>
+<li>The Reassociation pass (<tt>-reassociate</tt>) can now
+ factor expressions, e.g. turning "A*A+A*B" into "A*(A+B)".</li>
+<li>Several LLVM passes are <a href="http://llvm.org/PR681">significantly
+faster</a>.</li>
+</ul>
</div>
+<!--_________________________________________________________________________-->
+<div class="doc_subsubsection"><a name="codgennew">Code Generator
+Improvements</a></div>
-<!--=========================================================================-->
-<div class="doc_subsection">
-<a name="codequality">Code Generator Improvements in LLVM 1.6</a>
+<div class="doc_text">
+<ul>
+<li>LLVM has a new prepass (before register allocation) list scheduler, which
+ supports bottom-up and top-down scheduling, pluggable priority functions and
+ pluggable hazard recognizers. The X86 backend uses this to reduce register
+ pressure and RISC targets schedule based on operation latency.</li>
+<li>The tblgen-based target description framework introduced in LLVM 1.6 has
+ several new features, useful for targets that can fold loads and stores into
+ operations, and features that make the .td files more expressive.</li>
+<li>The instruction selector is significantly faster in 1.7 than in 1.6.</li>
+<li>The X86, Alpha and Itanium backends use new DAG-DAG instruction selectors,
+ making them easier to maintain and generate slightly better code.</li>
+<li>The X86 backend now supports generation of Scalar SSE code for scalar FP
+ expressions. LLVM provides significantly better performance with Scalar SSE
+ instructions than it does with the Intel floating point stack
+ instructions.</li>
+<li>The Itanium backend now has a bundling pass, which improves performance
+ by ~10% and reduces code size (previously it unconditionally inserted a stop
+ bit after every instruction).</li>
+</ul>
</div>
+<!--_________________________________________________________________________-->
+<div class="doc_subsubsection"><a name="othernew">Other New Features</a></div>
+
<div class="doc_text">
-<ol>
-<li>The Alpha backend is substantially more stable and robust than in LLVM 1.5.
- For example, it now fully supports varargs functions. The Alpha backend
- also now features beta JIT support.</li>
-<li>The code generator contains a new component, the DAG Combiner. This allows
- us to optimize lowered code (e.g. after 64-bit operations have been lowered
- to use 32-bit registers on 32-bit targets) and do fine-grained bit-twiddling
- optimizations for the backend.</li>
-<li>The SelectionDAG infrastructure is far more capable and mature, able to
- handle many new target peculiarities in a target-independent way.</li>
-<li>The default <a href="http://llvm.org/PR547">register allocator is now far
- faster on some testcases</a>,
- particularly on targets with a large number of registers (e.g. IA64
- and PPC).</li>
-</ol>
+<ul>
+<li>The Mac OS/X PowerPC and X86 backends now have initial support for
+ Darwin DWARF
+ debugging information, however, debug info generation has been disabled for
+ the 1.7 release in llvmgcc4.</li>
+<li>LLVM includes the new <a href="docs/CommandGuide/html/llvm-config.html">
+ llvm-config</a> utility, which makes it easier to build and link programs
+ against the LLVM libraries when not using the LLVM makefiles.</li>
+<li>LLVM now supports first class global ctor/dtor initialization lists, no
+ longer forcing targets to use "__main".</li>
+<li>LLVM supports assigning globals and functions to a particular section
+ in the result executable using the GCC section attribute.</li>
+<li><a href="ExtendingLLVM.html">Adding intrinsics to LLVM</a> is now
+ significantly easier.</li>
+<li>llvmgcc4 now fully supports C99 Variable Length Arrays, including dynamic
+ stack deallocation.</li>
+
+</ul>
</div>
+
<!--=========================================================================-->
<div class="doc_subsection">
-<a name="bugfix">Significant Bugs Fixed in LLVM 1.6</a>
+<a name="changes">Significant Changes in LLVM 1.7</a>
</div>
<div class="doc_text">
-<ol>
- <li>A vast number of bugs have been fixed in the PowerPC backend and in
- llvm-gcc when configured for Mac OS/X (particularly relating to ABI
- issues). For example:
- <a href="http://llvm.org/PR603">PR449</a>,
- <a href="http://llvm.org/PR594">PR594</a>,
- <a href="http://llvm.org/PR603">PR603</a>,
- <a href="http://llvm.org/PR609">PR609</a>,
- <a href="http://llvm.org/PR630">PR630</a>,
- <a href="http://llvm.org/PR643">PR643</a>,
- and several others without bugzilla bugs.</li>
- <li>Several bugs in tail call support have been fixed.</li>
- <li><a href="http://llvm.org/PR608">configure does not correctly detect gcc
- version on cygwin</a>.</li>
- <li>Many many other random bugs have been fixed. Query <a
- href="http://llvm.org/bugs">our bugzilla</a> with a target of 1.6 for more
- information.</li>
-</ol>
+<ul>
+<li>The official LLVM URL is now <a href="http://llvm.org/">
+ http://llvm.org/</a>.</li>
+<li>The LLVM intrinsics used to be overloaded based on type: for example,
+ <a href="LangRef.html#int_ctpop"><tt>llvm.ctpop</tt></a> could work with any
+ integer datatype. They are now separated into different intrinsics with
+ suffixes to denote their argument type (e.g. <tt>llvm.ctpop.i32</tt>)). Old
+ LLVM .ll and .bc files that use these intrinsics will continue to work with
+ new LLVM versions (they are transparently upgraded by the parsers), but will
+ cause a warning to be emitted.</li>
+<li>The <tt>llvm.readport</tt>, <tt>llvm.writeport</tt>, <tt>llvm.readio</tt>,
+ and <tt>llvm.writeio</tt> intrinsics have been removed. The first two
+ were ever only supported by the X86 backend, the last two were never
+ correctly supported by any target, and none were accessible through the
+ C front-end. Inline assembly support can now be used to
+ implement these operations.</li>
+<li>The <tt>llvm-db</tt> tool had basic support for stepping through code, which
+ used the JIT. This code has been removed, and DWARF emission support added
+ instead. <tt>llvm-db</tt> still exists in CVS if someone wanted to write a
+ <tt>ptrace</tt> backend for it.</li>
+</ul>
</div>
+
<!-- *********************************************************************** -->
<div class="doc_section">
<a name="portability">Portability and Supported Platforms</a>
components, please contact us on the llvmdev list.</p>
<ul>
-<li>The following passes are incomplete or buggy, and may be removed in future
- releases: <tt>-cee, -pre</tt></li>
-<li>The <tt>llvm-db</tt> tool is in a very early stage of development, but can
- be used to step through programs and inspect the stack.</li>
-<li>The SparcV8 and IA64 code generators are experimental.</li>
+<li>The <tt>-cee</tt> pass is known to be buggy, and may be removed in in a
+ future release.</li>
+<li>The IA64 code generator is experimental.</li>
<li>The Alpha JIT is experimental.</li>
+<li>"<tt>-filetype=asm</tt>" (the default) is the only supported value for the
+ <tt>-filetype</tt> llc option.</li>
</ul>
</div>
+<!-- ======================================================================= -->
+<div class="doc_subsection">
+ <a name="build">Known problems with the Build System</a>
+</div>
+
+<div class="doc_text">
+
+<ul>
+<li>none yet</li>
+</ul>
+</div>
+
+
<!-- ======================================================================= -->
<div class="doc_subsection">
<a name="core">Known problems with the LLVM Core</a>
<div class="doc_subsubsection">Bugs</div>
<div class="doc_text">
+
+<p>
+llvm-gcc3 has many significant problems that are fixed by llvm-gcc4. See
+ those blocked on the <a href="http://llvm.org/PR498">llvm-gcc4 meta bug</a>.
+Two major ones include:</p>
+
<ul>
-<li>C99 Variable sized arrays do not release stack memory when they go out of
+<li>With llvm-gcc3,
+ C99 variable sized arrays do not release stack memory when they go out of
scope. Thus, the following program may run out of stack space:
<pre>
for (i = 0; i != 1000000; ++i) {
}
</pre></li>
-<li>Initialization of global union variables can only be done <a
+<li>With llvm-gcc3, Initialization of global union variables can only be done <a
href="http://llvm.org/PR162">with the largest union member</a>.</li>
</ul>
<ul>
-<li>Inline assembly is not yet supported.</li>
-
<li>"long double" is transformed by the front-end into "double". There is no
support for floating point data types of any size other than 32 and 64
bits.</li>
<b>Supported:</b> <tt>format</tt>, <tt>format_arg</tt>, <tt>non_null</tt>,
<tt>noreturn</tt>, <tt>constructor</tt>, <tt>destructor</tt>,
- <tt>unused</tt>,
+ <tt>unused</tt>, <tt>used</tt>,
<tt>deprecated</tt>, <tt>warn_unused_result</tt>, <tt>weak</tt><br>
<b>Ignored:</b> <tt>noinline</tt>,
<tt>always_inline</tt>, <tt>pure</tt>, <tt>const</tt>, <tt>nothrow</tt>,
<tt>malloc</tt>, <tt>no_instrument_function</tt>, <tt>cdecl</tt><br>
- <b>Unsupported:</b> <tt>used</tt>, <tt>section</tt>, <tt>alias</tt>,
+ <b>Unsupported:</b> <tt>section</tt>, <tt>alias</tt>,
<tt>visibility</tt>, <tt>regparm</tt>, <tt>stdcall</tt>,
<tt>fastcall</tt>, all other target specific attributes</li>
Specifying attributes of variables.<br>
<b>Supported:</b> <tt>cleanup</tt>, <tt>common</tt>, <tt>nocommon</tt>,
<tt>deprecated</tt>, <tt>transparent_union</tt>,
- <tt>unused</tt>, <tt>weak</tt><br>
+ <tt>unused</tt>, <tt>used</tt>, <tt>weak</tt><br>
<b>Unsupported:</b> <tt>aligned</tt>, <tt>mode</tt>, <tt>packed</tt>,
<tt>section</tt>, <tt>shared</tt>, <tt>tls_model</tt>,
<ul>
-<li>The C++ front-end is based on a pre-release of the GCC 3.4 C++ parser. This
-parser is significantly more standards compliant (and picky) than prior GCC
-versions. For more information, see the C++ section of the <a
-href="http://gcc.gnu.org/gcc-3.4/changes.html">GCC 3.4 release notes</a>.</li>
-
<li>Destructors for local objects are not always run when a <tt>longjmp</tt> is
performed. In particular, destructors for objects in the <tt>longjmp</tt>ing
function and in the <tt>setjmp</tt> receiver function may not be run.
supported</a>. This should not affect LLVM produced by the C or C++
frontends.</li>
+<li>The C backend does not correctly implement the <a
+href="LangRef.html#i_stacksave"><tt>llvm.stacksave</tt></a> or
+<a href="LangRef.html#i_stackrestore"><tt>llvm.stackrestore</tt></a>
+intrinsics. This means that some code compiled by it can run out of stack
+space if they depend on these (e.g. C99 varargs).</li>
+
</ul>
</div>
<div class="doc_text">
<ul>
-<li><a href="http://llvm.org/PR566">Memory Mapped I/O Intrinsics do not fence
-memory</a></li>
+<li><a href="http://llvm.org/PR736">Indirect calls crash JIT on
+Darwin/x86</a>.</li>
</ul>
</div>
<div class="doc_text">
<ul>
-<li>None yet</li>
-</ul>
-
-</div>
-
-<!-- ======================================================================= -->
-<div class="doc_subsection">
- <a name="sparcv9-be">Known problems with the SparcV9 back-end</a>
-</div>
-
-<div class="doc_text">
-
-<ul>
-<li><a href="http://llvm.org/PR60">[sparcv9] SparcV9 backend miscompiles
-several programs in the LLVM test suite</a></li>
+<li><a href="http://llvm.org/PR642">PowerPC backend does not correctly
+implement ordered FP comparisons</a>.</li>
</ul>
</div>
<!-- ======================================================================= -->
<div class="doc_subsection">
- <a name="sparcv8">Known problems with the SPARC-V8 back-end</a>
+ <a name="sparc-be">Known problems with the SPARC back-end</a>
+</div>
+
+<div class="doc_text">
+
+<ul>
+<li>The SPARC backend only supports the 32-bit SPARC ABI (-m32), it does not
+ support the 64-bit SPARC ABI (-m64).</li>
+</ul>
+
+</div>
+
+
+<!-- ======================================================================= -->
+<div class="doc_subsection">
+ <a name="sparcv9-be">Known problems with the SparcV9 back-end</a>
</div>
<div class="doc_text">
<ul>
-<li>Many features are still missing (e.g. support for 64-bit integer
-arithmetic). This back-end is in pre-beta state.</li>
+<li><a href="http://llvm.org/PR60">[sparcv9] SparcV9 backend miscompiles
+several programs in the LLVM test suite</a></li>
+<li>The SparcV9 backend is slated to be removed before the LLVM 1.8
+ release.</li>
</ul>
+
</div>
<!-- *********************************************************************** -->