<b>bit</b> mayLoad = 0;
<b>bit</b> mayStore = 0;
<b>bit</b> isImplicitDef = 0;
- <b>bit</b> isTwoAddress = 1;
<b>bit</b> isConvertibleToThreeAddress = 1;
<b>bit</b> isCommutable = 1;
<b>bit</b> isTerminator = 0;
<b>bit</b> hasCtrlDep = 0;
<b>bit</b> isNotDuplicable = 0;
<b>bit</b> hasSideEffects = 0;
- <b>bit</b> mayHaveSideEffects = 0;
<b>bit</b> neverHasSideEffects = 0;
InstrItinClass Itinerary = NoItinerary;
<b>string</b> Constraints = "";
<p>As you can see, a lot of information is needed for every instruction
supported by the code generator, and specifying it all manually would be
-unmaintainble, prone to bugs, and tiring to do in the first place. Because we
+unmaintainable, prone to bugs, and tiring to do in the first place. Because we
are using TableGen, all of the information was derived from the following
definition:</p>
<dd>This type represents a nestable directed graph of elements.</dd>
<dt><tt><b>code</b></tt></dt>
- <dd>This represents a big hunk of text. NOTE: I don't remember why this is
- distinct from string!</dd>
+ <dd>This represents a big hunk of text. This is lexically distinct from
+ string values because it doesn't require escapeing double quotes and other
+ common characters that occur in code.</dd>
</dl>
<p>To date, these types have been sufficient for describing things that
the symbol table. If the type of 'a' does not match <em>type</em>, TableGen
aborts with an error. !cast<string> is a special case in that the argument must
be an object defined by a 'def' construct.</dd>
-<dt><tt>!nameconcat<type>(a, b)</tt></dt>
- <dd>Shorthand for !cast<type>(!strconcat(a, b))</dd>
<dt><tt>!subst(a, b, c)</tt></dt>
<dd>If 'a' and 'b' are of string type or are symbol references, substitute
'b' for 'a' in 'c.' This operation is analogous to $(subst) in GNU make.</dd>
<dt><tt>!null(a)</tt></dt>
<dd>An integer {0,1} indicating whether list 'a' is empty.</dd>
<dt><tt>!if(a,b,c)</tt></dt>
- <dd>'b' if the result of integer operator 'a' is nonzero, 'c' otherwise.</dd>
+ <dd>'b' if the result of 'int' or 'bit' operator 'a' is nonzero,
+ 'c' otherwise.</dd>
+<dt><tt>!eq(a,b)</tt></dt>
+ <dd>'bit 1' if string a is equal to string b, 0 otherwise. This
+ only operates on string, int and bit objects. Use !cast<string> to
+ compare other types of objects.</dd>
</dl>
<p>Note that all of the values have rules specifying how they convert to values
</pre>
</div>
+<p>
+A defm can also be used inside a multiclass providing several levels of
+multiclass instanciations.
+</p>
+
+<div class="doc_code">
+<pre>
+<b>class</b> Instruction<bits<4> opc, string Name> {
+ bits<4> opcode = opc;
+ string name = Name;
+}
+
+<b>multiclass</b> basic_r<bits<4> opc> {
+ <b>def</b> rr : Instruction<opc, "rr">;
+ <b>def</b> rm : Instruction<opc, "rm">;
+}
+
+<b>multiclass</b> basic_s<bits<4> opc> {
+ <b>defm</b> SS : basic_r<opc>;
+ <b>defm</b> SD : basic_r<opc>;
+ <b>def</b> X : Instruction<opc, "x">;
+}
+
+<b>multiclass</b> basic_p<bits<4> opc> {
+ <b>defm</b> PS : basic_r<opc>;
+ <b>defm</b> PD : basic_r<opc>;
+ <b>def</b> Y : Instruction<opc, "y">;
+}
+
+<b>defm</b> ADD : basic_s<0xf>, basic_p<0xf>;
+...
+
+<i>// Results</i>
+<b>def</b> ADDPDrm { ...
+<b>def</b> ADDPDrr { ...
+<b>def</b> ADDPSrm { ...
+<b>def</b> ADDPSrr { ...
+<b>def</b> ADDSDrm { ...
+<b>def</b> ADDSDrr { ...
+<b>def</b> ADDY { ...
+<b>def</b> ADDX { ...
+</pre>
+</div>
+
+<p>
+defm declarations can inherit from classes too, the
+rule to follow is that the class list must start after the
+last multiclass, and there must be at least one multiclass
+before them.
+</p>
+
+<div class="doc_code">
+<pre>
+<b>class</b> XD { bits<4> Prefix = 11; }
+<b>class</b> XS { bits<4> Prefix = 12; }
+
+<b>class</b> I<bits<4> op> {
+ bits<4> opcode = op;
+}
+
+<b>multiclass</b> R {
+ <b>def</b> rr : I<4>;
+ <b>def</b> rm : I<2>;
+}
+
+<b>multiclass</b> Y {
+ <b>defm</b> SS : R, XD;
+ <b>defm</b> SD : R, XS;
+}
+
+<b>defm</b> Instr : Y;
+
+<i>// Results</i>
+<b>def</b> InstrSDrm {
+ bits<4> opcode = { 0, 0, 1, 0 };
+ bits<4> Prefix = { 1, 1, 0, 0 };
+}
+...
+<b>def</b> InstrSSrr {
+ bits<4> opcode = { 0, 1, 0, 0 };
+ bits<4> Prefix = { 1, 0, 1, 1 };
+}
+</pre>
+</div>
+
</div>
<!-- ======================================================================= -->
apply, and one or more records to bind the values in. Here are some
examples:</p>
-<div class="doc_code">
-<pre>
+<pre class="doc_code">
<b>let</b> isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep = 1 <b>in</b>
<b>def</b> RET : I<0xC3, RawFrm, (outs), (ins), "ret", [(X86retflag 0)]>;
"call\t{*}$dst", []>;
}
</pre>
-</div>
<p>File-scope "let" expressions are often useful when a couple of definitions
need to be added to several records, and the records do not otherwise need to be
opened, as in the case with the <tt>CALL*</tt> instructions above.</p>
+<p>It's also possible to use "let" expressions inside multiclasses, providing
+more ways to factor out commonality from the records, specially if using
+several levels of multiclass instanciations. This also avoids the need of using
+"let" expressions within subsequent records inside a multiclass.</p>
+
+<pre class="doc_code">
+<b>multiclass </b>basic_r<bits<4> opc> {
+ <b>let </b>Predicates = [HasSSE2] in {
+ <b>def </b>rr : Instruction<opc, "rr">;
+ <b>def </b>rm : Instruction<opc, "rm">;
+ }
+ <b>let </b>Predicates = [HasSSE3] in
+ <b>def </b>rx : Instruction<opc, "rx">;
+}
+
+<b>multiclass </b>basic_ss<bits<4> opc> {
+ <b>let </b>IsDouble = 0 in
+ <b>defm </b>SS : basic_r<opc>;
+
+ <b>let </b>IsDouble = 1 in
+ <b>defm </b>SD : basic_r<opc>;
+}
+
+<b>defm </b>ADD : basic_ss<0xf>;
+</pre>
</div>
<!-- *********************************************************************** -->
<div class="doc_section"><a name="codegen">Code Generator backend info</a></div>
<!-- *********************************************************************** -->
+<div class="doc_text">
+
<p>Expressions used by code generator to describe instructions and isel
patterns:</p>
-<div class="doc_text">
-
+<dl>
<dt><tt>(implicit a)</tt></dt>
<dd>an implicitly defined physical register. This tells the dag instruction
selection emitter the input pattern's extra definitions matches implicit
physical register definitions.</dd>
-<dt><tt>(parallel (a), (b))</tt></dt>
- <dd>a list of dags specifying parallel operations which map to the same
- instruction.</dd>
-
+</dl>
</div>
<!-- *********************************************************************** -->
projects / oota-llvm.git / blobdiff