</ul></li>
<li><a href="#InstructionSet">Instruction Set</a>
<ul>
+ <li><a href="#operandMapping">Instruction Operand Mapping</a></li>
<li><a href="#implementInstr">Implement a subclass of TargetInstrInfo</a></li>
<li><a href="#branchFolding">Branch Folding and If Conversion</a></li>
</ul></li>
<tt>SparcInstrInfo.td</tt>; that is, <tt>SPCC::ICC_NE = 9</tt>, <tt>SPCC::FCC_U = 23</tt> and so on.)</p>
</div>
+<!-- ======================================================================= -->
+<div class="doc_subsection">
+ <a name="operandMapping">Instruction Operand Mapping</a>
+</div>
+<div class="doc_text">
+<p>The code generator backend maps instruction operands to fields in
+the instruction. Operands are assigned to unbound fields in the instruction in
+the order they are defined. Fields are bound when they are assigned a value.
+For example, the Sparc target defines the XNORrr instruction as a F3_1 format
+instruction having three operands.</p>
+</div>
+
+<div class="doc_code"> <pre>
+def XNORrr : F3_1<2, 0b000111,
+ (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
+ "xnor $b, $c, $dst",
+ [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>;
+</pre></div>
+
+<div class="doc_text">
+<p>The instruction templates in <tt>SparcInstrFormats.td</tt> show the base class for F3_1 is InstSP.</p>
+</div>
+
+<div class="doc_code"> <pre>
+class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction {
+ field bits<32> Inst;
+ let Namespace = "SP";
+ bits<2> op;
+ let Inst{31-30} = op;
+ dag OutOperandList = outs;
+ dag InOperandList = ins;
+ let AsmString = asmstr;
+ let Pattern = pattern;
+}
+</pre></div>
+<div class="doc_text">
+<p>
+InstSP leaves the op field unbound.
+</p>
+</div>
+
+<div class="doc_code"> <pre>
+class F3<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstSP<outs, ins, asmstr, pattern> {
+ bits<5> rd;
+ bits<6> op3;
+ bits<5> rs1;
+ let op{1} = 1; // Op = 2 or 3
+ let Inst{29-25} = rd;
+ let Inst{24-19} = op3;
+ let Inst{18-14} = rs1;
+}
+</pre></div>
+<div class="doc_text">
+<p>
+F3 binds the op field and defines the rd, op3, and rs1 fields. F3 format instructions will
+bind the operands rd, op3, and rs1 fields.
+</p>
+</div>
+
+<div class="doc_code"> <pre>
+class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
+ string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
+ bits<8> asi = 0; // asi not currently used
+ bits<5> rs2;
+ let op = opVal;
+ let op3 = op3val;
+ let Inst{13} = 0; // i field = 0
+ let Inst{12-5} = asi; // address space identifier
+ let Inst{4-0} = rs2;
+}
+</pre></div>
+<div class="doc_text">
+<p>
+F3_1 binds the op3 field and defines the rs2 fields. F3_1 format instructions will
+bind the operands to the rd, rs1, and rs2 fields. This results in the XNORrr instruction
+binding $dst, $b, and $c operands to the rd, rs1, and rs2 fields respectively.
+</p>
+</div>
+
+
+
<!-- ======================================================================= -->
<div class="doc_subsection">
<a name="implementInstr">Implement a subclass of </a>
</div>
<div class="doc_code">
-<pre>SDNode *SelectCode(SDOperand N) {
+<pre>SDNode *SelectCode(SDValue N) {
...
- MVT::ValueType NVT = N.Val->getValueType(0);
+ MVT::ValueType NVT = N.getNode()->getValueType(0);
switch (N.getOpcode()) {
case ISD::STORE: {
switch (NVT) {
</div>
<div class="doc_code">
-<pre>SDNode *Select_ISD_STORE(const SDOperand &N) {
- SDOperand Chain = N.getOperand(0);
- if (Predicate_store(N.Val)) {
- SDOperand N1 = N.getOperand(1);
- SDOperand N2 = N.getOperand(2);
- SDOperand CPTmp0;
- SDOperand CPTmp1;
+<pre>SDNode *Select_ISD_STORE(const SDValue &N) {
+ SDValue Chain = N.getOperand(0);
+ if (Predicate_store(N.getNode())) {
+ SDValue N1 = N.getOperand(1);
+ SDValue N2 = N.getOperand(2);
+ SDValue CPTmp0;
+ SDValue CPTmp1;
// Pattern: (st:void IntRegs:i32:$src,
// ADDRrr:i32:$addr)<<P:Predicate_store>>
// Emits: (STrr:void ADDRrr:i32:$addr, IntRegs:i32:$src)
// Pattern complexity = 13 cost = 1 size = 0
if (SelectADDRrr(N, N2, CPTmp0, CPTmp1) &&
- N1.Val->getValueType(0) == MVT::i32 &&
- N2.Val->getValueType(0) == MVT::i32) {
+ N1.getNode()->getValueType(0) == MVT::i32 &&
+ N2.getNode()->getValueType(0) == MVT::i32) {
return Emit_22(N, SP::STrr, CPTmp0, CPTmp1);
}
...
</div>
<div class="doc_code">
-<pre>SDOperand SparcTargetLowering::LowerOperation(
- SDOperand Op, SelectionDAG &DAG) {
+<pre>SDValue SparcTargetLowering::LowerOperation(
+ SDValue Op, SelectionDAG &DAG) {
switch (Op.getOpcode()) {
case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
...
</div>
<div class="doc_code">
-<pre>static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
+<pre>static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
assert(Op.getValueType() == MVT::i32);
Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
<hr>
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<a href="http://www.woo.com">Mason Woo</a> and <a href="http://misha.brukman.net">Misha Brukman</a><br>
<a href="http://llvm.org">The LLVM Compiler Infrastructure</a>