Minor cleanup related to my latest scheduler changes.

[oota-llvm.git] / docs / WritingAnLLVMBackend.html

diff --git a/docs/WritingAnLLVMBackend.html b/docs/WritingAnLLVMBackend.html
index d909a1a3fb72e5b1774929aa42f92ef7a7a90c93..729023240de9a5ce2e209a87943ccd149b4ecdfe 100644 (file)
--- a/docs/WritingAnLLVMBackend.html
+++ b/docs/WritingAnLLVMBackend.html
@@ -1299,9 +1299,6 @@ implementation in <tt>SparcInstrInfo.cpp</tt>:
 </p>
 
 <ul>
-<li><tt>isMoveInstr</tt> &mdash; Return true if the instruction is a register to
-    register move; false, otherwise.</li>
-
 <li><tt>isLoadFromStackSlot</tt> &mdash; If the specified machine instruction is
     a direct load from a stack slot, return the register number of the
     destination and the <tt>FrameIndex</tt> of the stack slot.</li>
@@ -1310,7 +1307,8 @@ implementation in <tt>SparcInstrInfo.cpp</tt>:
     a direct store to a stack slot, return the register number of the
     destination and the <tt>FrameIndex</tt> of the stack slot.</li>
 
-<li><tt>copyRegToReg</tt> &mdash; Copy values between a pair of registers.</li>
+<li><tt>copyPhysReg</tt> &mdash; Copy values between a pair of physical
+    registers.</li>
 
 <li><tt>storeRegToStackSlot</tt> &mdash; Store a register value to a stack
     slot.</li>
@@ -1827,7 +1825,7 @@ register to convert the floating-point value to an integer.
 static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &amp;DAG) {
   assert(Op.getValueType() == MVT::i32);
   Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
-  return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
+  return DAG.getNode(ISD::BITCAST, MVT::i32, Op);
 }
 </pre>
 </div>