<li><a href="#Preliminaries">Preliminaries</a></li>
</ul>
<li><a href="#TargetMachine">Target Machine</a></li>
- <li><a href="#RegisterSet">Register Set and Register Classes</a></li>
+ <li><a href="#RegisterSet">Register Set and Register Classes</a>
<ul>
<li><a href="#RegisterDef">Defining a Register</a></li>
<li><a href="#RegisterClassDef">Defining a Register Class</a></li>
<li><a href="#implementRegister">Implement a subclass of TargetRegisterInfo</a></li>
- </ul>
- <li><a href="#InstructionSet">Instruction Set</a></li>
+ </ul></li>
+ <li><a href="#InstructionSet">Instruction Set</a>
<ul>
+ <li><a href="#operandMapping">Instruction Operand Mapping</a></li>
<li><a href="#implementInstr">Implement a subclass of TargetInstrInfo</a></li>
<li><a href="#branchFolding">Branch Folding and If Conversion</a></li>
- </ul>
- <li><a href="#InstructionSelector">Instruction Selector</a></li>
+ </ul></li>
+ <li><a href="#InstructionSelector">Instruction Selector</a>
<ul>
- <li><a href="#LegalizePhase">The SelectionDAG Legalize Phase</a></li>
+ <li><a href="#LegalizePhase">The SelectionDAG Legalize Phase</a>
<ul>
<li><a href="#promote">Promote</a></li>
<li><a href="#expand">Expand</a></li>
<li><a href="#custom">Custom</a></li>
<li><a href="#legal">Legal</a></li>
- </ul>
+ </ul></li>
<li><a href="#callingConventions">Calling Conventions</a></li>
- </ul>
+ </ul></li>
<li><a href="#assemblyPrinter">Assembly Printer</a></li>
<li><a href="#subtargetSupport">Subtarget Support</a></li>
- <li><a href="#jitSupport">JIT Support</a></li>
+ <li><a href="#jitSupport">JIT Support</a>
<ul>
<li><a href="#mce">Machine Code Emitter</a></li>
<li><a href="#targetJITInfo">Target JIT Info</a></li>
- </ul>
+ </ul></li>
</ol>
<div class="doc_author">
These essential documents must be read before reading this document:
<ul>
<li>
-<it><a href="http://www.llvm.org/docs/LangRef.html">LLVM Language Reference Manual</a></it> -
+<i><a href="http://www.llvm.org/docs/LangRef.html">LLVM Language Reference Manual</a></i> -
a reference manual for the LLVM assembly language
</li>
<li>
-<it><a href="http://www.llvm.org/docs/CodeGenerator.html">The LLVM Target-Independent Code Generator </a></it> -
+<i><a href="http://www.llvm.org/docs/CodeGenerator.html">The LLVM Target-Independent Code Generator </a></i> -
a guide to the components (classes and code generation algorithms) for translating
the LLVM internal representation to the machine code for a specified target.
Pay particular attention to the descriptions of code generation stages:
and Code Emission.
</li>
<li>
-<it><a href="http://www.llvm.org/docs/TableGenFundamentals.html">TableGen Fundamentals</a></it> -
+<i><a href="http://www.llvm.org/docs/TableGenFundamentals.html">TableGen Fundamentals</a></i> -
a document that describes the TableGen (tblgen) application that manages domain-specific
information to support LLVM code generation. TableGen processes input from a
target description file (.td suffix) and generates C++ code that can be used
for code generation.
</li>
<li>
-<it><a href="http://www.llvm.org/docs/WritingAnLLVMPass.html">Writing an LLVM Pass</a></it> -
+<i><a href="http://www.llvm.org/docs/WritingAnLLVMPass.html">Writing an LLVM Pass</a></i> -
The assembly printer is a FunctionPass, as are several SelectionDAG processing steps.
</li>
</ul>
To follow the SPARC examples in this document, have a copy of
-<it><a href="http://www.sparc.org/standards/V8.pdf">The SPARC Architecture Manual, Version 8</a></it>
+<i><a href="http://www.sparc.org/standards/V8.pdf">The SPARC Architecture Manual, Version 8</a></i>
for reference. For details about the ARM instruction set, refer to the
-<it><a href="http://infocenter.arm.com/">ARM Architecture Reference Manual</a></it>
+<i><a href="http://infocenter.arm.com/">ARM Architecture Reference Manual</a></i>
For more about the GNU Assembler format (GAS), see
-<it><a href="http://sourceware.org/binutils/docs/as/index.html">Using As</a></it>
-especially for the assembly printer. <it>Using As</it> contains lists of target machine dependent features.
+<i><a href="http://sourceware.org/binutils/docs/as/index.html">Using As</a></i>
+especially for the assembly printer. <i>Using As</i> contains lists of target machine dependent features.
</div>
<div class="doc_subsection">
</div>
<!-- ======================================================================= -->
<div class="doc_subsection">
- <a name="implementRegister">Implement a subclass of
- <a href="http://www.llvm.org/docs/CodeGenerator.html#targetregisterinfo">TargetRegisterInfo</a></a>
+ <a name="implementRegister">Implement a subclass of</a>
+ <a href="http://www.llvm.org/docs/CodeGenerator.html#targetregisterinfo">TargetRegisterInfo</a>
</div>
<div class="doc_text">
<p>The final step is to hand code portions of XXXRegisterInfo, which
<!-- ======================================================================= -->
<div class="doc_subsection">
- <a name="implementInstr">Implement a subclass of
- <a href="http://www.llvm.org/docs/CodeGenerator.html#targetinstrinfo">TargetInstrInfo</a></a>
+ <a name="operandMapping">Instruction Operand Mapping</a>
+</div>
+<div class="doc_text">
+<p>The code generator backend maps instruction operands to fields in
+the instruction. Operands are assigned to unbound fields in the instruction in
+the order they are defined. Fields are bound when they are assigned a value.
+For example, the Sparc target defines the XNORrr instruction as a F3_1 format
+instruction having three operands.</p>
+</div>
+
+<div class="doc_code"> <pre>
+def XNORrr : F3_1<2, 0b000111,
+ (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
+ "xnor $b, $c, $dst",
+ [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>;
+</pre></div>
+
+<div class="doc_text">
+<p>The instruction templates in <tt>SparcInstrFormats.td</tt> show the base class for F3_1 is InstSP.</p>
+</div>
+
+<div class="doc_code"> <pre>
+class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction {
+ field bits<32> Inst;
+ let Namespace = "SP";
+ bits<2> op;
+ let Inst{31-30} = op;
+ dag OutOperandList = outs;
+ dag InOperandList = ins;
+ let AsmString = asmstr;
+ let Pattern = pattern;
+}
+</pre></div>
+<div class="doc_text">
+<p>
+InstSP leaves the op field unbound.
+</p>
+</div>
+
+<div class="doc_code"> <pre>
+class F3<dag outs, dag ins, string asmstr, list<dag> pattern>
+ : InstSP<outs, ins, asmstr, pattern> {
+ bits<5> rd;
+ bits<6> op3;
+ bits<5> rs1;
+ let op{1} = 1; // Op = 2 or 3
+ let Inst{29-25} = rd;
+ let Inst{24-19} = op3;
+ let Inst{18-14} = rs1;
+}
+</pre></div>
+<div class="doc_text">
+<p>
+F3 binds the op field and defines the rd, op3, and rs1 fields. F3 format instructions will
+bind the operands rd, op3, and rs1 fields.
+</p>
+</div>
+
+<div class="doc_code"> <pre>
+class F3_1<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
+ string asmstr, list<dag> pattern> : F3<outs, ins, asmstr, pattern> {
+ bits<8> asi = 0; // asi not currently used
+ bits<5> rs2;
+ let op = opVal;
+ let op3 = op3val;
+ let Inst{13} = 0; // i field = 0
+ let Inst{12-5} = asi; // address space identifier
+ let Inst{4-0} = rs2;
+}
+</pre></div>
+<div class="doc_text">
+<p>
+F3_1 binds the op3 field and defines the rs2 fields. F3_1 format instructions will
+bind the operands to the rd, rs1, and rs2 fields. This results in the XNORrr instruction
+binding $dst, $b, and $c operands to the rd, rs1, and rs2 fields respectively.
+</p>
+</div>
+
+
+
+<!-- ======================================================================= -->
+<div class="doc_subsection">
+ <a name="implementInstr">Implement a subclass of </a>
+ <a href="http://www.llvm.org/docs/CodeGenerator.html#targetinstrinfo">TargetInstrInfo</a>
</div>
<div class="doc_text">
<p>You should examine the node types in the ISD namespace
(<tt>include/llvm/CodeGen/SelectionDAGNodes.h</tt>)
and determine which operations the target natively supports. For operations
-that do <u>not</u> have native support, add a callback to the constructor for
+that do <b>not</b> have native support, add a callback to the constructor for
the XXXTargetLowering class, so the instruction selection process knows what to
do. The TargetLowering class callback methods (declared in
<tt>llvm/Target/TargetLowering.h</tt>) are:</p>
</div>
<div class="doc_text">
<p>The <tt>Legal</tt> LegalizeAction enum value simply indicates that an
-operation <u>is</u> natively supported. <tt>Legal</tt> represents the default condition,
+operation <b>is</b> natively supported. <tt>Legal</tt> represents the default condition,
so it is rarely used. In <tt>SparcISelLowering.cpp</tt>, the action for CTPOP (an
operation to count the bits set in an integer) is natively supported only for
SPARC v9. The following code enables the <tt>Expand</tt> conversion technique for non-v9
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<a href="http://www.woo.com">Mason Woo</a> and <a href="http://misha.brukman.net">Misha Brukman</a><br>
<a href="http://llvm.org">The LLVM Compiler Infrastructure</a>
projects / oota-llvm.git / blobdiff