Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[firefly-linux-kernel-4.4.55.git] / drivers / bcma / driver_chipcommon_pmu.c
index c62c788b3289f0d338667dfd3ecaa4f50d39ada6..edca73af3cc089fd342573ec0fca20bcc5ddc677 100644 (file)
@@ -174,19 +174,35 @@ u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc)
        struct bcma_bus *bus = cc->core->bus;
 
        switch (bus->chipinfo.id) {
+       case BCMA_CHIP_ID_BCM4313:
+       case BCMA_CHIP_ID_BCM43224:
+       case BCMA_CHIP_ID_BCM43225:
+       case BCMA_CHIP_ID_BCM43227:
+       case BCMA_CHIP_ID_BCM43228:
+       case BCMA_CHIP_ID_BCM4331:
+       case BCMA_CHIP_ID_BCM43421:
+       case BCMA_CHIP_ID_BCM43428:
+       case BCMA_CHIP_ID_BCM43431:
        case BCMA_CHIP_ID_BCM4716:
-       case BCMA_CHIP_ID_BCM4748:
        case BCMA_CHIP_ID_BCM47162:
-       case BCMA_CHIP_ID_BCM4313:
-       case BCMA_CHIP_ID_BCM5357:
+       case BCMA_CHIP_ID_BCM4748:
        case BCMA_CHIP_ID_BCM4749:
+       case BCMA_CHIP_ID_BCM5357:
        case BCMA_CHIP_ID_BCM53572:
+       case BCMA_CHIP_ID_BCM6362:
                /* always 20Mhz */
                return 20000 * 1000;
-       case BCMA_CHIP_ID_BCM5356:
        case BCMA_CHIP_ID_BCM4706:
+       case BCMA_CHIP_ID_BCM5356:
                /* always 25Mhz */
                return 25000 * 1000;
+       case BCMA_CHIP_ID_BCM43460:
+       case BCMA_CHIP_ID_BCM4352:
+       case BCMA_CHIP_ID_BCM4360:
+               if (cc->status & BCMA_CC_CHIPST_4360_XTAL_40MZ)
+                       return 40000 * 1000;
+               else
+                       return 20000 * 1000;
        default:
                bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
                          bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
@@ -264,7 +280,7 @@ static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
 }
 
 /* query bus clock frequency for PMU-enabled chipcommon */
-static u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
+u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
 {
        struct bcma_bus *bus = cc->core->bus;
 
@@ -293,6 +309,7 @@ static u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
        }
        return BCMA_CC_PMU_HT_CLOCK;
 }
+EXPORT_SYMBOL_GPL(bcma_pmu_get_bus_clock);
 
 /* query cpu clock frequency for PMU-enabled chipcommon */
 u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc)
@@ -372,7 +389,7 @@ void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid)
                tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
                bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
 
-               tmp = 1 << 10;
+               tmp = BCMA_CC_PMU_CTL_PLL_UPD;
                break;
 
        case BCMA_CHIP_ID_BCM4331:
@@ -393,7 +410,7 @@ void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid)
                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
                                                     0x03000a08);
                }
-               tmp = 1 << 10;
+               tmp = BCMA_CC_PMU_CTL_PLL_UPD;
                break;
 
        case BCMA_CHIP_ID_BCM43224:
@@ -426,7 +443,7 @@ void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid)
                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
                                                     0x88888815);
                }
-               tmp = 1 << 10;
+               tmp = BCMA_CC_PMU_CTL_PLL_UPD;
                break;
 
        case BCMA_CHIP_ID_BCM4716:
@@ -460,7 +477,7 @@ void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid)
                                                     0x88888815);
                }
 
-               tmp = 3 << 9;
+               tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
                break;
 
        case BCMA_CHIP_ID_BCM43227:
@@ -496,7 +513,7 @@ void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid)
                        bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
                                                     0x88888815);
                }
-               tmp = 1 << 10;
+               tmp = BCMA_CC_PMU_CTL_PLL_UPD;
                break;
        default:
                bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",