drm/plane: Remove redundant extern

[firefly-linux-kernel-4.4.55.git] / drivers / clk / ingenic / jz4740-cgu.c

diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c
index 0209ed6d412a9960a21f1b19c2d68fdf0724a6b2..305a26c2a800ec621806f7cf9df71bf66e881bb3 100644 (file)
--- a/drivers/clk/ingenic/jz4740-cgu.c
+++ b/drivers/clk/ingenic/jz4740-cgu.c
@@ -26,6 +26,7 @@
 #define CGU_REG_CPCCR          0x00
 #define CGU_REG_LCR            0x04
 #define CGU_REG_CPPCR          0x10
+#define CGU_REG_CLKGR          0x20
 #define CGU_REG_SCR            0x24
 #define CGU_REG_I2SCDR         0x60
 #define CGU_REG_LPCDR          0x64
@@ -47,6 +48,9 @@
 /* bits within the LCR register */
 #define LCR_SLEEP              (1 << 0)
 
+/* bits within the CLKGR register */
+#define CLKGR_UDC              (1 << 11)
+
 static struct ingenic_cgu *cgu;
 
 static const s8 pll_od_encoding[4] = {
@@ -242,3 +246,58 @@ void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode)
 
        writel(lcr, cgu->base + CGU_REG_LCR);
 }
+
+void jz4740_clock_udc_disable_auto_suspend(void)
+{
+       uint32_t clkgr = readl(cgu->base + CGU_REG_CLKGR);
+
+       clkgr &= ~CLKGR_UDC;
+       writel(clkgr, cgu->base + CGU_REG_CLKGR);
+}
+EXPORT_SYMBOL_GPL(jz4740_clock_udc_disable_auto_suspend);
+
+void jz4740_clock_udc_enable_auto_suspend(void)
+{
+       uint32_t clkgr = readl(cgu->base + CGU_REG_CLKGR);
+
+       clkgr |= CLKGR_UDC;
+       writel(clkgr, cgu->base + CGU_REG_CLKGR);
+}
+EXPORT_SYMBOL_GPL(jz4740_clock_udc_enable_auto_suspend);
+
+#define JZ_CLOCK_GATE_UART0    BIT(0)
+#define JZ_CLOCK_GATE_TCU      BIT(1)
+#define JZ_CLOCK_GATE_DMAC     BIT(12)
+
+void jz4740_clock_suspend(void)
+{
+       uint32_t clkgr, cppcr;
+
+       clkgr = readl(cgu->base + CGU_REG_CLKGR);
+       clkgr |= JZ_CLOCK_GATE_TCU | JZ_CLOCK_GATE_DMAC | JZ_CLOCK_GATE_UART0;
+       writel(clkgr, cgu->base + CGU_REG_CLKGR);
+
+       cppcr = readl(cgu->base + CGU_REG_CPPCR);
+       cppcr &= ~BIT(jz4740_cgu_clocks[JZ4740_CLK_PLL].pll.enable_bit);
+       writel(cppcr, cgu->base + CGU_REG_CPPCR);
+}
+
+void jz4740_clock_resume(void)
+{
+       uint32_t clkgr, cppcr, stable;
+
+       cppcr = readl(cgu->base + CGU_REG_CPPCR);
+       cppcr |= BIT(jz4740_cgu_clocks[JZ4740_CLK_PLL].pll.enable_bit);
+       writel(cppcr, cgu->base + CGU_REG_CPPCR);
+
+       stable = BIT(jz4740_cgu_clocks[JZ4740_CLK_PLL].pll.stable_bit);
+       do {
+               cppcr = readl(cgu->base + CGU_REG_CPPCR);
+       } while (!(cppcr & stable));
+
+       clkgr = readl(cgu->base + CGU_REG_CLKGR);
+       clkgr &= ~JZ_CLOCK_GATE_TCU;
+       clkgr &= ~JZ_CLOCK_GATE_DMAC;
+       clkgr &= ~JZ_CLOCK_GATE_UART0;
+       writel(clkgr, cgu->base + CGU_REG_CLKGR);
+}