clk: qcom: Add support for setting rates on PLLs

[firefly-linux-kernel-4.4.55.git] / drivers / clk / qcom / clk-pll.h

diff --git a/drivers/clk/qcom/clk-pll.h b/drivers/clk/qcom/clk-pll.h
index 3003e9962472f3ae98ae55709d2d4f347d2ccf40..c9c0cda306d04e45548daa0d5b50f802ab2c04a9 100644 (file)
--- a/drivers/clk/qcom/clk-pll.h
+++ b/drivers/clk/qcom/clk-pll.h
@@ -17,6 +17,21 @@
 #include <linux/clk-provider.h>
 #include "clk-regmap.h"
 
+/**
+ * struct pll_freq_tbl - PLL frequency table
+ * @l: L value
+ * @m: M value
+ * @n: N value
+ * @ibits: internal values
+ */
+struct pll_freq_tbl {
+       unsigned long freq;
+       u16 l;
+       u16 m;
+       u16 n;
+       u32 ibits;
+};
+
 /**
  * struct clk_pll - phase locked loop (PLL)
  * @l_reg: L register
@@ -26,6 +41,7 @@
  * @mode_reg: mode register
  * @status_reg: status register
  * @status_bit: ANDed with @status_reg to determine if PLL is enabled
+ * @freq_tbl: PLL frequency table
  * @hw: handle between common and hardware-specific interfaces
  */
 struct clk_pll {
@@ -36,6 +52,10 @@ struct clk_pll {
        u32     mode_reg;
        u32     status_reg;
        u8      status_bit;
+       u8      post_div_width;
+       u8      post_div_shift;
+
+       const struct pll_freq_tbl *freq_tbl;
 
        struct clk_regmap clkr;
 };