Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...

[firefly-linux-kernel-4.4.55.git] / drivers / clk / ux500 / clk.h

diff --git a/drivers/clk/ux500/clk.h b/drivers/clk/ux500/clk.h
index c3e449169a83ce9841fb977a9a2732e22a27c70b..a2bb92d85ee0a980ad458745f93c2ca00acf4266 100644 (file)
--- a/drivers/clk/ux500/clk.h
+++ b/drivers/clk/ux500/clk.h
@@ -11,16 +11,18 @@
 #define __UX500_CLK_H
 
 #include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/types.h>
 
 struct clk *clk_reg_prcc_pclk(const char *name,
                              const char *parent_name,
-                             unsigned int phy_base,
+                             resource_size_t phy_base,
                              u32 cg_sel,
                              unsigned long flags);
 
 struct clk *clk_reg_prcc_kclk(const char *name,
                              const char *parent_name,
-                             unsigned int phy_base,
+                             resource_size_t phy_base,
                              u32 cg_sel,
                              unsigned long flags);
 
@@ -57,4 +59,32 @@ struct clk *clk_reg_prcmu_opp_volt_scalable(const char *name,
                                            unsigned long rate,
                                            unsigned long flags);
 
+struct clk *clk_reg_sysctrl_gate(struct device *dev,
+                                const char *name,
+                                const char *parent_name,
+                                u16 reg_sel,
+                                u8 reg_mask,
+                                u8 reg_bits,
+                                unsigned long enable_delay_us,
+                                unsigned long flags);
+
+struct clk *clk_reg_sysctrl_gate_fixed_rate(struct device *dev,
+                                           const char *name,
+                                           const char *parent_name,
+                                           u16 reg_sel,
+                                           u8 reg_mask,
+                                           u8 reg_bits,
+                                           unsigned long rate,
+                                           unsigned long enable_delay_us,
+                                           unsigned long flags);
+
+struct clk *clk_reg_sysctrl_set_parent(struct device *dev,
+                                      const char *name,
+                                      const char **parent_names,
+                                      u8 num_parents,
+                                      u16 *reg_sel,
+                                      u8 *reg_mask,
+                                      u8 *reg_bits,
+                                      unsigned long flags);
+
 #endif /* __UX500_CLK_H */