Merge branch 'kconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/mmarek/kbuild

[firefly-linux-kernel-4.4.55.git] / drivers / edac / amd64_edac.c

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index d6c0c6590607b4c732cec7e7114864d66ab00126..3c9e4e98c65111a069dcbcc5916cd2e061052938 100644 (file)
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -206,8 +206,8 @@ static int amd64_set_scrub_rate(struct mem_ctl_info *mci, u32 bw)
        if (pvt->fam == 0xf)
                min_scrubrate = 0x0;
 
-       /* Erratum #505 for F15h Model 0x00 - Model 0x01, Stepping 0 */
-       if (pvt->fam == 0x15 && pvt->model <= 0x01 && pvt->stepping < 0x1)
+       /* Erratum #505 */
+       if (pvt->fam == 0x15 && pvt->model < 0x10)
                f15h_select_dct(pvt, 0);
 
        return __amd64_set_scrub_rate(pvt->F3, bw, min_scrubrate);
@@ -219,8 +219,8 @@ static int amd64_get_scrub_rate(struct mem_ctl_info *mci)
        u32 scrubval = 0;
        int i, retval = -EINVAL;
 
-       /* Erratum #505 for F15h Model 0x00 - Model 0x01, Stepping 0 */
-       if (pvt->fam == 0x15 && pvt->model <= 0x01 && pvt->stepping < 0x1)
+       /* Erratum #505 */
+       if (pvt->fam == 0x15 && pvt->model < 0x10)
                f15h_select_dct(pvt, 0);
 
        amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval);
@@ -1558,11 +1558,12 @@ static int f15_m30h_match_to_this_node(struct amd64_pvt *pvt, unsigned range,
        }
 
        /* Verify sys_addr is within DCT Range. */
-       dct_base = (dct_sel_baseaddr(pvt) << 27);
-       dct_limit = (((dct_cont_limit_reg >> 11) & 0x1FFF) << 27) | 0x7FFFFFF;
+       dct_base = (u64) dct_sel_baseaddr(pvt);
+       dct_limit = (dct_cont_limit_reg >> 11) & 0x1FFF;
 
        if (!(dct_cont_base_reg & BIT(0)) &&
-           !(dct_base <= sys_addr && dct_limit >= sys_addr))
+           !(dct_base <= (sys_addr >> 27) &&
+             dct_limit >= (sys_addr >> 27)))
                return -EINVAL;
 
        /* Verify number of dct's that participate in channel interleaving. */
@@ -1584,7 +1585,7 @@ static int f15_m30h_match_to_this_node(struct amd64_pvt *pvt, unsigned range,
        if (leg_mmio_hole && (sys_addr >= BIT_64(32)))
                chan_offset = dhar_offset;
        else
-               chan_offset = dct_base;
+               chan_offset = dct_base << 27;
 
        chan_addr = sys_addr - chan_offset;
 
@@ -1614,7 +1615,7 @@ static int f15_m30h_match_to_this_node(struct amd64_pvt *pvt, unsigned range,
                amd64_read_pci_cfg(pvt->F1,
                                   DRAM_CONT_HIGH_OFF + (int) channel * 4,
                                   &tmp);
-               chan_addr +=  ((tmp >> 11) & 0xfff) << 27;
+               chan_addr +=  (u64) ((tmp >> 11) & 0xfff) << 27;
        }
 
        f15h_select_dct(pvt, channel);
@@ -2642,8 +2643,15 @@ static int amd64_init_one_instance(struct pci_dev *F2)
        layers[0].size = pvt->csels[0].b_cnt;
        layers[0].is_virt_csrow = true;
        layers[1].type = EDAC_MC_LAYER_CHANNEL;
-       layers[1].size = pvt->channel_count;
+
+       /*
+        * Always allocate two channels since we can have setups with DIMMs on
+        * only one channel. Also, this simplifies handling later for the price
+        * of a couple of KBs tops.
+        */
+       layers[1].size = 2;
        layers[1].is_virt_csrow = false;
+
        mci = edac_mc_alloc(nid, ARRAY_SIZE(layers), layers, 0);
        if (!mci)
                goto err_siblings;