#include <linux/i2c.h>\r
#include <mach/rk2818_iomap.h>\r
\r
-#include "spi_fpga.h"\r
+#include <mach/spi_fpga.h>\r
\r
#if defined(CONFIG_SPI_FPGA_INIT_DEBUG)\r
#define DBG(x...) printk(x)\r
#else\r
#define DBG(x...)\r
#endif\r
+\r
struct spi_fpga_port *pFpgaPort;\r
\r
/*------------------------spi¶ÁдµÄ»ù±¾º¯Êý-----------------------*/\r
unsigned int spi_in(struct spi_fpga_port *port, int reg, int type)\r
{\r
unsigned char index = 0;\r
- unsigned char tx_buf[1], rx_buf[2], n_rx=2, stat=0;\r
+ unsigned char tx_buf[2], rx_buf[2], n_rx=2, stat=0;\r
unsigned int result=0;\r
//printk("index1=%d\n",index);\r
\r
index = port->uart.index;\r
reg = (((reg) | ICE_SEL_UART) | ICE_SEL_READ | ICE_SEL_UART_CH(index));\r
tx_buf[0] = reg & 0xff;\r
+ tx_buf[1] = 0;\r
rx_buf[0] = 0;\r
rx_buf[1] = 0; \r
- stat = spi_write_then_read(port->spi, (const u8 *)&tx_buf, sizeof(tx_buf), rx_buf, n_rx);\r
- result = rx_buf[1];\r
+ stat = spi_write_then_read(port->spi, (const u8 *)&tx_buf, sizeof(tx_buf)-1, rx_buf, n_rx);\r
+ result = (rx_buf[0] << 8) | rx_buf[1];\r
DBG("%s,SEL_UART reg=0x%x,result=0x%x\n",__FUNCTION__,reg&0xff,result&0xff);\r
break;\r
#endif\r
case SEL_GPIO:\r
reg = (((reg) | ICE_SEL_GPIO) | ICE_SEL_READ );\r
tx_buf[0] = reg & 0xff;\r
+ tx_buf[1] = 0;//give fpga 8 clks for reading data\r
rx_buf[0] = 0;\r
rx_buf[1] = 0; \r
stat = spi_write_then_read(port->spi, (const u8 *)&tx_buf, sizeof(tx_buf), rx_buf, n_rx);\r
\r
#if defined(CONFIG_SPI_I2C)\r
case SEL_I2C:\r
- reg = (((reg) | ICE_SEL_I2C) & ICE_SEL_READ );\r
+ reg = (((reg) | ICE_SEL_I2C) | ICE_SEL_READ );\r
tx_buf[0] = reg & 0xff;\r
+ tx_buf[1] = 0;\r
rx_buf[0] = 0;\r
rx_buf[1] = 0; \r
- stat = spi_write_then_read(port->spi, (const u8 *)&tx_buf, sizeof(tx_buf), rx_buf, n_rx);\r
- result = (rx_buf[0] << 8) | rx_buf[1];\r
- DBG("%s,SEL_I2C reg=0x%x,result=0x%x [0x%x] [0x%x]\n",__FUNCTION__,reg&0xff,result&0xffff,rx_buf[0],rx_buf[1]); \r
+ stat = spi_write_then_read(port->spi, (const u8 *)&tx_buf, sizeof(tx_buf)-1, rx_buf, n_rx);\r
+ result = rx_buf[1];\r
+ DBG("%s,SEL_I2C reg=0x%x,result=0x%x \n",__FUNCTION__,reg&0xff,result&0xffff); \r
break;\r
#endif\r
\r
case SEL_DPRAM:\r
reg = (((reg) | ICE_SEL_DPRAM) & ICE_SEL_DPRAM_READ );\r
tx_buf[0] = reg & 0xff;\r
+ tx_buf[1] = 0;//give fpga 8 clks for reading data\r
rx_buf[0] = 0;\r
rx_buf[1] = 0; \r
stat = spi_write_then_read(port->spi, (const u8 *)&tx_buf, sizeof(tx_buf), rx_buf, n_rx);\r
DBG("%s,SEL_GPIO reg=0x%x,result=0x%x\n",__FUNCTION__,reg&0xff,result&0xffff); \r
break;\r
#endif\r
+ case READ_TOP_INT:\r
+ reg = (((reg) | ICE_SEL_UART) | ICE_SEL_READ);\r
+ tx_buf[0] = reg & 0xff;\r
+ tx_buf[1] = 0;\r
+ rx_buf[0] = 0;\r
+ rx_buf[1] = 0; \r
+ stat = spi_write_then_read(port->spi, (const u8 *)&tx_buf, sizeof(tx_buf)-1, rx_buf, n_rx);\r
+ result = rx_buf[1];\r
+ DBG("%s,SEL_INT reg=0x%x,result=0x%x\n",__FUNCTION__,reg&0xff,result&0xff);\r
+ break;\r
default:\r
- printk("Can not support this type!\n");\r
+ printk("%s err: Can not support this type!\n",__FUNCTION__);\r
break;\r
}\r
\r
#endif\r
\r
#if defined(CONFIG_SPI_I2C)\r
-\r
case SEL_I2C:\r
reg = (((reg) | ICE_SEL_I2C) & ICE_SEL_WRITE);\r
tx_buf[0] = reg & 0xff;\r
#endif\r
\r
default:\r
- printk("Can not support this type!\n");\r
+ printk("%s err: Can not support this type!\n",__FUNCTION__);\r
break;\r
}\r
\r
}\r
\r
+#if SPI_FPGA_TEST_DEBUG\r
+int spi_test_wrong_handle(void)\r
+{\r
+ gpio_direction_output(SPI_FPGA_TEST_DEBUG_PIN,0);\r
+ udelay(2);\r
+ gpio_direction_output(SPI_FPGA_TEST_DEBUG_PIN,1);\r
+ printk("%s:give one trailing edge!\n",__FUNCTION__);\r
+ return 0;\r
+}\r
+\r
+static int spi_test_request_gpio(int set)\r
+{\r
+ int ret;\r
+ rk2818_mux_api_set(GPIOE0_VIPDATA0_SEL_NAME,0);\r
+ ret = gpio_request(SPI_FPGA_TEST_DEBUG_PIN, NULL);\r
+ if (ret) {\r
+ printk("%s:failed to request SPI_FPGA_TEST_DEBUG_PIN pin\n",__FUNCTION__);\r
+ return ret;\r
+ } \r
+ gpio_direction_output(SPI_FPGA_TEST_DEBUG_PIN,set);\r
+\r
+ return 0;\r
+}\r
+\r
+#endif\r
\r
static void spi_fpga_irq_work_handler(struct work_struct *work)\r
{\r
struct spi_fpga_port *port =\r
container_of(work, struct spi_fpga_port, fpga_irq_work);\r
struct spi_device *spi = port->spi;\r
- int ret,uart_ch,gpio_ch;\r
+ int ret,uart_ch=0;\r
\r
DBG("Enter::%s,LINE=%d\n",__FUNCTION__,__LINE__);\r
\r
- ret = spi_in(port, ICE_SEL_READ_INT_TYPE, SEL_UART);\r
+ ret = spi_in(port, ICE_SEL_READ_INT_TYPE, READ_TOP_INT);\r
if((ret | ICE_INT_TYPE_UART0) == ICE_INT_TYPE_UART0)\r
{\r
#if defined(CONFIG_SPI_UART)\r
- uart_ch = 0;\r
- printk("Enter::%s,LINE=%d,uart_ch=%d,uart.index=%d\n",__FUNCTION__,__LINE__,uart_ch,port->uart.index);\r
+ DBG("%s:ICE_INT_TYPE_UART0 ret=0x%x\n",__FUNCTION__,ret);\r
port->uart.index = uart_ch;\r
spi_uart_handle_irq(spi);\r
#endif\r
}\r
else if((ret | ICE_INT_TYPE_GPIO) == ICE_INT_TYPE_GPIO)\r
{\r
- gpio_ch = 0;\r
- printk("Enter::%s,LINE=%d,gpio_ch=%d\n",__FUNCTION__,__LINE__,gpio_ch);\r
#if defined(CONFIG_SPI_GPIO)\r
+ printk("%s:ICE_INT_TYPE_GPIO ret=0x%x\n",__FUNCTION__,ret);\r
spi_gpio_handle_irq(spi);\r
#endif\r
}\r
else if((ret | ICE_INT_TYPE_I2C2) == ICE_INT_TYPE_I2C2)\r
{\r
#if defined(CONFIG_SPI_I2C)\r
- spi_i2c_handle_irq(port,0);\r
+ DBG("%s:ICE_INT_TYPE_I2C2 ret=0x%x\n",__FUNCTION__,ret);\r
+ spi_i2c_handle_irq(port,I2C_CH2);\r
#endif\r
}\r
else if((ret | ICE_INT_TYPE_I2C3) == ICE_INT_TYPE_I2C3)\r
{\r
#if defined(CONFIG_SPI_I2C)\r
- spi_i2c_handle_irq(port,1);\r
+ DBG("%s:ICE_INT_TYPE_I2C3 ret=0x%x\n",__FUNCTION__,ret);\r
+ spi_i2c_handle_irq(port,I2C_CH3);\r
#endif\r
}\r
else if((ret | ICE_INT_TYPE_DPRAM) == ICE_INT_TYPE_DPRAM)\r
{\r
#if defined(CONFIG_SPI_DPRAM)\r
+ DBG("%s:ICE_INT_TYPE_DPRAM ret=0x%x\n",__FUNCTION__,ret);\r
spi_dpram_handle_irq(spi);\r
#endif\r
}\r
else\r
{\r
- printk("%s:NO such INT TYPE\n",__FUNCTION__);\r
+ printk("%s:NO such INT TYPE,ret=0x%x\n",__FUNCTION__,ret);\r
}\r
\r
DBG("Enter::%s,LINE=%d\n",__FUNCTION__,__LINE__);\r
return 0;\r
}\r
\r
-\r
+extern int spi_i2c_set_bt_power(void);\r
static int __devinit spi_fpga_probe(struct spi_device * spi)\r
{\r
struct spi_fpga_port *port;\r
int ret;\r
char b[12];\r
+ int num;\r
DBG("Enter::%s,LINE=%d************************\n",__FUNCTION__,__LINE__);\r
/*\r
* bits_per_word cannot be configured in platform data\r
return ret;\r
}\r
#endif\r
-#if 0 //defined(CONFIG_SPI_I2C)\r
+#if defined(CONFIG_SPI_I2C)\r
\r
printk("%s:line=%d,port=0x%x\n",__FUNCTION__,__LINE__,(int)port);\r
- ret = spi_i2c_register(port);\r
- printk("%s:line=%d,port=0x%x\n",__FUNCTION__,__LINE__,(int)port);\r
- if(ret)\r
+ spin_lock_init(&port->i2c.i2c_lock);\r
+ for (num= 2;num<4;num++)\r
{\r
- spi_i2c_unregister(port);\r
- printk("%s:ret=%d,fail to spi_i2c_register\n",__FUNCTION__,ret);\r
- return ret;\r
+ ret = spi_i2c_register(port,num);\r
+ printk("%s:line=%d,port=0x%x\n",__FUNCTION__,__LINE__,(int)port);\r
+ if(ret)\r
+ {\r
+ spi_i2c_unregister(port);\r
+ printk("%s:ret=%d,fail to spi_i2c_register\n",__FUNCTION__,ret);\r
+ return ret;\r
+ }\r
}\r
#endif\r
+\r
#if defined(CONFIG_SPI_DPRAM)\r
ret = spi_dpram_register(port);\r
if(ret)\r
spi_gpio_init();\r
#endif\r
\r
+#if SPI_FPGA_TEST_DEBUG\r
+ spi_test_request_gpio(GPIO_HIGH);\r
+#endif\r
+\r
return 0;\r
\r
err2:\r
projects / firefly-linux-kernel-4.4.55.git / blobdiff