Merge tag 'drm-intel-fixes-2015-07-15' into drm-intel-next-queued

[firefly-linux-kernel-4.4.55.git] / drivers / gpu / drm / i915 / i915_debugfs.c

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 73aaea22bbef1103680020888ab5decc9ab707ab..bc817da9fef7a05c37c2f67b50c52b21725b3663 100644 (file)
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1732,12 +1732,15 @@ static int i915_sr_status(struct seq_file *m, void *unused)
 
        if (HAS_PCH_SPLIT(dev))
                sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
-       else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
+       else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
+                IS_I945G(dev) || IS_I945GM(dev))
                sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
        else if (IS_I915GM(dev))
                sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
        else if (IS_PINEVIEW(dev))
                sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
+       else if (IS_VALLEYVIEW(dev))
+               sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
 
        intel_runtime_pm_put(dev_priv);
 
@@ -1782,8 +1785,9 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
        struct drm_i915_private *dev_priv = dev->dev_private;
        int ret = 0;
        int gpu_freq, ia_freq;
+       unsigned int max_gpu_freq, min_gpu_freq;
 
-       if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
+       if (!HAS_CORE_RING_FREQ(dev)) {
                seq_puts(m, "unsupported on this chipset\n");
                return 0;
        }
@@ -1796,17 +1800,27 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
        if (ret)
                goto out;
 
+       if (IS_SKYLAKE(dev)) {
+               /* Convert GT frequency to 50 HZ units */
+               min_gpu_freq =
+                       dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
+               max_gpu_freq =
+                       dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
+       } else {
+               min_gpu_freq = dev_priv->rps.min_freq_softlimit;
+               max_gpu_freq = dev_priv->rps.max_freq_softlimit;
+       }
+
        seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
 
-       for (gpu_freq = dev_priv->rps.min_freq_softlimit;
-            gpu_freq <= dev_priv->rps.max_freq_softlimit;
-            gpu_freq++) {
+       for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
                ia_freq = gpu_freq;
                sandybridge_pcode_read(dev_priv,
                                       GEN6_PCODE_READ_MIN_FREQ_TABLE,
                                       &ia_freq);
                seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
-                          intel_gpu_freq(dev_priv, gpu_freq),
+                          intel_gpu_freq(dev_priv, (gpu_freq *
+                               (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1))),
                           ((ia_freq >> 0) & 0xff) * 100,
                           ((ia_freq >> 8) & 0xff) * 100);
        }