drm/i915: Work around DISPLAY_PHY_CONTROL register corruption on CHV

[firefly-linux-kernel-4.4.55.git] / drivers / gpu / drm / i915 / i915_drv.h

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index df46e2735991db12bcf084be6a621fb967446f57..1321956ec066f9f5bec928b317e5bbbc169f59b6 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -238,6 +238,11 @@ enum hpd_pin {
 #define for_each_crtc(dev, crtc) \
        list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 
+#define for_each_intel_plane(dev, intel_plane) \
+       list_for_each_entry(intel_plane,                        \
+                           &dev->mode_config.plane_list,       \
+                           base.head)
+
 #define for_each_intel_crtc(dev, intel_crtc) \
        list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
 
@@ -295,7 +300,7 @@ struct intel_dpll_hw_state {
        /* skl */
        /*
         * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
-        * lower part of crtl1 and they get shifted into position when writing
+        * lower part of ctrl1 and they get shifted into position when writing
         * the register.  This allows us to easily compare the state to share
         * the DPLL.
         */
@@ -669,6 +674,12 @@ struct intel_uncore {
 #define for_each_fw_domain(domain__, dev_priv__, i__) \
        for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
 
+enum csr_state {
+       FW_UNINITIALIZED = 0,
+       FW_LOADED,
+       FW_FAILED
+};
+
 struct intel_csr {
        const char *fw_path;
        __be32 *dmc_payload;
@@ -676,6 +687,7 @@ struct intel_csr {
        uint32_t mmio_count;
        uint32_t mmioaddr[8];
        uint32_t mmiodata[8];
+       enum csr_state state;
 };
 
 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
@@ -1357,7 +1369,6 @@ struct intel_vbt_data {
        bool edp_initialized;
        bool edp_support;
        int edp_bpp;
-       bool edp_low_vswing;
        struct edp_power_seq edp_pps;
 
        struct {
@@ -1771,6 +1782,8 @@ struct drm_i915_private {
 
        u32 fdi_rx_config;
 
+       u32 chv_phy_control;
+
        u32 suspend_count;
        struct i915_suspend_saved_registers regfile;
        struct vlv_s0ix_state vlv_s0ix_state;
@@ -1839,6 +1852,8 @@ struct drm_i915_private {
                void (*stop_ring)(struct intel_engine_cs *ring);
        } gt;
 
+       bool edp_low_vswing;
+
        /*
         * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
         * will be rejected. Instead look for a better place.
@@ -2436,7 +2451,8 @@ struct drm_i915_cmd_table {
                                 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
                                 IS_SKYLAKE(dev))
 #define HAS_RUNTIME_PM(dev)    (IS_GEN6(dev) || IS_HASWELL(dev) || \
-                                IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
+                                IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
+                                IS_SKYLAKE(dev))
 #define HAS_RC6(dev)           (INTEL_INFO(dev)->gen >= 6)
 #define HAS_RC6p(dev)          (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
 
@@ -2507,6 +2523,7 @@ struct i915_params {
        int mmio_debug;
        bool verbose_state_checks;
        bool nuclear_pageflip;
+       int edp_vswing;
 };
 extern struct i915_params i915 __read_mostly;