drm/i915: manage PCH PLLs separately from pipes

[firefly-linux-kernel-4.4.55.git] / drivers / gpu / drm / i915 / i915_drv.h

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index faea1b6568217f5bc3127d460448cc865134ad1e..c1440137002ac94f832a3f87a87192355a98d199 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -78,6 +78,16 @@ enum port {
 
 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
 
+struct intel_pch_pll {
+       int refcount; /* count of number of CRTCs sharing this PLL */
+       int active; /* count of number of active CRTCs (i.e. DPMS on) */
+       bool on; /* is the PLL actually active? Disabled during modeset */
+       int pll_reg;
+       int fp0_reg;
+       int fp1_reg;
+};
+#define I915_NUM_PLLS 2
+
 /* Interface history:
  *
  * 1.1: Original.
@@ -233,6 +243,7 @@ struct drm_i915_display_funcs {
                             struct drm_display_mode *adjusted_mode,
                             int x, int y,
                             struct drm_framebuffer *old_fb);
+       void (*off)(struct drm_crtc *crtc);
        void (*write_eld)(struct drm_connector *connector,
                          struct drm_crtc *crtc);
        void (*fdi_link_train)(struct drm_crtc *crtc);
@@ -391,6 +402,7 @@ typedef struct drm_i915_private {
        unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
        int vblank_pipe;
        int num_pipe;
+       int num_pch_pll;
 
        /* For hangcheck timer */
 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
@@ -753,6 +765,8 @@ typedef struct drm_i915_private {
        wait_queue_head_t pending_flip_queue;
        bool flip_pending_is_done;
 
+       struct intel_pch_pll pch_plls[I915_NUM_PLLS];
+
        /* Reclocking support */
        bool render_reclock_avail;
        bool lvds_downclock_avail;