drm/i915: Use a common seqno for all rings.

[firefly-linux-kernel-4.4.55.git] / drivers / gpu / drm / i915 / i915_drv.h

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 70e252768ab3b8bbb699e94dcef3ca73ccc8cfb9..def6ee0a352457f1019458b977c83850f27e9c58 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -113,6 +113,9 @@ struct intel_opregion {
        int enabled;
 };
 
+struct intel_overlay;
+struct intel_overlay_error_state;
+
 struct drm_i915_master_private {
        drm_local_map_t *sarea;
        struct _drm_i915_sarea *sarea_priv;
@@ -166,6 +169,7 @@ struct drm_i915_error_state {
                u32 purgeable:1;
        } *active_bo;
        u32 active_bo_count;
+       struct intel_overlay_error_state *overlay;
 };
 
 struct drm_i915_display_funcs {
@@ -186,8 +190,6 @@ struct drm_i915_display_funcs {
        /* clock gating init */
 };
 
-struct intel_overlay;
-
 struct intel_device_info {
        u8 is_mobile : 1;
        u8 is_i8xx : 1;
@@ -201,6 +203,8 @@ struct intel_device_info {
        u8 need_gfx_hws : 1;
        u8 is_g4x : 1;
        u8 is_pineview : 1;
+       u8 is_broadwater : 1;
+       u8 is_crestline : 1;
        u8 is_ironlake : 1;
        u8 is_gen6 : 1;
        u8 has_fbc : 1;
@@ -216,6 +220,7 @@ enum no_fbc_reason {
        FBC_MODE_TOO_LARGE, /* mode too large for compression */
        FBC_BAD_PLANE, /* fbc not supported on plane */
        FBC_NOT_TILED, /* buffer not tiled */
+       FBC_MULTIPLE_PIPES, /* more than one pipe active */
 };
 
 enum intel_pch {
@@ -223,6 +228,8 @@ enum intel_pch {
        PCH_CPT,        /* Cougarpoint PCH */
 };
 
+#define QUIRK_PIPEA_FORCE (1<<0)
+
 struct intel_fbdev;
 
 typedef struct drm_i915_private {
@@ -237,6 +244,7 @@ typedef struct drm_i915_private {
        struct pci_dev *bridge_dev;
        struct intel_ring_buffer render_ring;
        struct intel_ring_buffer bsd_ring;
+       uint32_t next_seqno;
 
        drm_dma_handle_t *status_page_dmah;
        void *seqno_page;
@@ -280,6 +288,9 @@ typedef struct drm_i915_private {
        unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
        int vblank_pipe;
        int num_pipe;
+       u32 flush_rings;
+#define FLUSH_RENDER_RING      0x1
+#define FLUSH_BSD_RING         0x2
 
        /* For hangcheck timer */
 #define DRM_I915_HANGCHECK_PERIOD 75 /* in jiffies */
@@ -340,6 +351,8 @@ typedef struct drm_i915_private {
        /* PCH chipset type */
        enum intel_pch pch_type;
 
+       unsigned long quirks;
+
        /* Register state */
        bool modeset_on_lid;
        u8 saveLBB;
@@ -544,6 +557,14 @@ typedef struct drm_i915_private {
                /** LRU list of objects with fence regs on them. */
                struct list_head fence_list;
 
+               /**
+                * List of objects currently pending being freed.
+                *
+                * These objects are no longer in use, but due to a signal
+                * we were prevented from freeing them at the appointed time.
+                */
+               struct list_head deferred_free_list;
+
                /**
                 * We leave the user IRQ off as much as possible,
                 * but this means that requests will finish and never
@@ -553,8 +574,6 @@ typedef struct drm_i915_private {
                 */
                struct delayed_work retire_work;
 
-               uint32_t next_gem_seqno;
-
                /**
                 * Waiting sequence number, if any
                 */
@@ -953,8 +972,7 @@ uint32_t i915_get_gem_seqno(struct drm_device *dev,
 bool i915_seqno_passed(uint32_t seq1, uint32_t seq2);
 int i915_gem_object_get_fence_reg(struct drm_gem_object *obj);
 int i915_gem_object_put_fence_reg(struct drm_gem_object *obj);
-void i915_gem_retire_requests(struct drm_device *dev,
-                struct intel_ring_buffer *ring);
+void i915_gem_retire_requests(struct drm_device *dev);
 void i915_gem_retire_work_handler(struct work_struct *work);
 void i915_gem_clflush_object(struct drm_gem_object *obj);
 int i915_gem_object_set_domain(struct drm_gem_object *obj,
@@ -1052,6 +1070,10 @@ extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
 extern void intel_detect_pch (struct drm_device *dev);
 extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
 
+/* overlay */
+extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
+extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
+
 /**
  * Lock test for when it's just for synchronization of ring access.
  *
@@ -1078,26 +1100,26 @@ extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
 #define I915_VERBOSE 0
 
 #define BEGIN_LP_RING(n)  do { \
-       drm_i915_private_t *dev_priv = dev->dev_private;                \
+       drm_i915_private_t *dev_priv__ = dev->dev_private;                \
        if (I915_VERBOSE)                                               \
                DRM_DEBUG("   BEGIN_LP_RING %x\n", (int)(n));           \
-       intel_ring_begin(dev, &dev_priv->render_ring, (n));             \
+       intel_ring_begin(dev, &dev_priv__->render_ring, (n));           \
 } while (0)
 
 
 #define OUT_RING(x) do {                                               \
-       drm_i915_private_t *dev_priv = dev->dev_private;                \
+       drm_i915_private_t *dev_priv__ = dev->dev_private;              \
        if (I915_VERBOSE)                                               \
                DRM_DEBUG("   OUT_RING %x\n", (int)(x));                \
-       intel_ring_emit(dev, &dev_priv->render_ring, x);                \
+       intel_ring_emit(dev, &dev_priv__->render_ring, x);              \
 } while (0)
 
 #define ADVANCE_LP_RING() do {                                         \
-       drm_i915_private_t *dev_priv = dev->dev_private;                \
+       drm_i915_private_t *dev_priv__ = dev->dev_private;                \
        if (I915_VERBOSE)                                               \
                DRM_DEBUG("ADVANCE_LP_RING %x\n",                       \
-                               dev_priv->render_ring.tail);            \
-       intel_ring_advance(dev, &dev_priv->render_ring);                \
+                               dev_priv__->render_ring.tail);          \
+       intel_ring_advance(dev, &dev_priv__->render_ring);              \
 } while(0)
 
 /**
@@ -1134,6 +1156,8 @@ extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
 #define IS_I945GM(dev)         (INTEL_INFO(dev)->is_i945gm)
 #define IS_I965G(dev)          (INTEL_INFO(dev)->is_i965g)
 #define IS_I965GM(dev)         (INTEL_INFO(dev)->is_i965gm)
+#define IS_BROADWATER(dev)     (INTEL_INFO(dev)->is_broadwater)
+#define IS_CRESTLINE(dev)      (INTEL_INFO(dev)->is_crestline)
 #define IS_GM45(dev)           ((dev)->pci_device == 0x2A42)
 #define IS_G4X(dev)            (INTEL_INFO(dev)->is_g4x)
 #define IS_PINEVIEW_G(dev)     ((dev)->pci_device == 0xa001)