drm/i915: add intel_display_power_enabled

[firefly-linux-kernel-4.4.55.git] / drivers / gpu / drm / i915 / intel_display.c

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c48bb76c055c91be6cb8cfa76c2971f2934cc426..c46f40d88d8ec5710e77c27e32faa3daf7fd7ed5 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1110,8 +1110,8 @@ void assert_pipe(struct drm_i915_private *dev_priv,
        if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
                state = true;
 
-       if (!intel_using_power_well(dev_priv->dev) &&
-           cpu_transcoder != TRANSCODER_EDP) {
+       if (!intel_display_power_enabled(dev_priv->dev,
+                               POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
                cur_state = false;
        } else {
                reg = PIPECONF(cpu_transcoder);
@@ -3229,7 +3229,7 @@ prepare: /* separate function? */
        return pll;
 }
 
-void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
+static void cpt_verify_modeset(struct drm_device *dev, int pipe)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
        int dslreg = PIPEDSL(pipe);
@@ -3249,8 +3249,7 @@ static void ironlake_pfit_enable(struct intel_crtc *crtc)
        struct drm_i915_private *dev_priv = dev->dev_private;
        int pipe = crtc->pipe;
 
-       if (crtc->config.pch_pfit.size &&
-           intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) {
+       if (crtc->config.pch_pfit.size) {
                /* Force use of hard-coded filter coefficients
                 * as some pre-programmed values are broken,
                 * e.g. x201.
@@ -3334,7 +3333,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
                encoder->enable(encoder);
 
        if (HAS_PCH_CPT(dev))
-               intel_cpt_verify_modeset(dev, intel_crtc->pipe);
+               cpt_verify_modeset(dev, intel_crtc->pipe);
 
        /*
         * There seems to be a race in PCH platform hw (at least on some
@@ -3533,7 +3532,8 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
        /* XXX: Once we have proper panel fitter state tracking implemented with
         * hardware state read/check support we should switch to only disable
         * the panel fitter when we know it's used. */
-       if (intel_using_power_well(dev)) {
+       if (intel_display_power_enabled(dev,
+                                       POWER_DOMAIN_PIPE_PANEL_FITTER(pipe))) {
                I915_WRITE(PF_CTL(pipe), 0);
                I915_WRITE(PF_WIN_SZ(pipe), 0);
        }
@@ -4469,10 +4469,13 @@ static void vlv_update_pll(struct intel_crtc *crtc)
        mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
        mdiv |= ((bestn << DPIO_N_SHIFT));
        mdiv |= (1 << DPIO_K_SHIFT);
-       if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI) ||
-           intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
-           intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
-               mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
+
+       /*
+        * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
+        * but we don't support that).
+        * Note: don't use the DAC post divider as it seems unstable.
+        */
+       mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
        intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
 
        mdiv |= DPIO_ENABLE_CALIBRATION;
@@ -6037,8 +6040,8 @@ static bool haswell_get_pipe_config(struct intel_crtc *crtc,
        enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
        uint32_t tmp;
 
-       if (!intel_using_power_well(dev_priv->dev) &&
-           cpu_transcoder != TRANSCODER_EDP)
+       if (!intel_display_power_enabled(dev,
+                       POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
                return false;
 
        tmp = I915_READ(PIPECONF(cpu_transcoder));