drm/i915: Set AGPBUSY# bit in init_clock_gating

[firefly-linux-kernel-4.4.55.git] / drivers / gpu / drm / i915 / intel_pm.c

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index cca93d06894c4593012a0072f7f3096df35a26bc..71de9eec33812c9fe6d4bf99d63b86ebc89aebb9 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5504,6 +5504,9 @@ static void gen3_init_clock_gating(struct drm_device *dev)
 
        /* IIR "flip pending" means done if this bit is set */
        I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
+
+       /* interrupts should cause a wake up from C3 */
+       I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
 }
 
 static void i85x_init_clock_gating(struct drm_device *dev)
@@ -5711,9 +5714,11 @@ static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
 void __vlv_set_power_well(struct drm_i915_private *dev_priv,
                          enum punit_power_well power_well_id, bool enable)
 {
+       struct drm_device *dev = dev_priv->dev;
        u32 mask;
        u32 state;
        u32 ctrl;
+       enum pipe pipe;
 
        if (power_well_id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
                if (enable) {
@@ -5727,6 +5732,8 @@ void __vlv_set_power_well(struct drm_i915_private *dev_priv,
                                   DPLL_INTEGRATED_CRI_CLK_VLV);
                        udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
                } else {
+                       for_each_pipe(pipe)
+                               assert_pll_disabled(dev_priv, pipe);
                        /* Assert common reset */
                        I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) &
                                   ~DPIO_CMNRST);