Merge branch 'drm-init-cleanup' of git://people.freedesktop.org/~danvet/drm into...

[firefly-linux-kernel-4.4.55.git] / drivers / gpu / drm / i915 / intel_sideband.c

diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index cc6fbcde7d3d607f5b4adcb9f77e3cce29eee5ba..b1a5514e695a71d95b3a6b76522a1a119a41a4bd 100644 (file)
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -182,6 +182,14 @@ u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg)
 
        vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)),
                        DPIO_OPCODE_REG_READ, reg, &val);
+
+       /*
+        * FIXME: There might be some registers where all 1's is a valid value,
+        * so ideally we should check the register offset instead...
+        */
+       WARN(val == 0xffffffff, "DPIO read pipe %c reg 0x%x == 0x%x\n",
+            pipe_name(pipe), reg, val);
+
        return val;
 }
 
@@ -249,3 +257,17 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
                return;
        }
 }
+
+u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg)
+{
+       u32 val = 0;
+       vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI,
+                                       DPIO_OPCODE_REG_READ, reg, &val);
+       return val;
+}
+
+void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
+{
+       vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI,
+                                       DPIO_OPCODE_REG_WRITE, reg, &val);
+}