struct panel_simple *p = to_panel_simple(panel);
int num = 0;
+ /* add device node plane modes */
+ num += panel_simple_of_get_native_mode(p);
+
+ /* add hard-coded panel modes */
+ num += panel_simple_get_fixed_modes(p);
+
/* probe EDID if a DDC bus is available */
if (p->ddc) {
struct edid *edid = drm_get_edid(panel->connector, p->ddc);
}
}
- /* add hard-coded panel modes */
- num += panel_simple_get_fixed_modes(p);
-
- /* add device node plane modes */
- num += panel_simple_of_get_native_mode(p);
-
return num;
}
{
struct device_node *backlight, *ddc;
struct panel_simple *panel;
+ struct panel_desc *of_desc;
+ u32 val;
int err;
panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
if (!panel)
return -ENOMEM;
+ if (!desc)
+ of_desc = devm_kzalloc(dev, sizeof(*of_desc), GFP_KERNEL);
+ else
+ of_desc = devm_kmemdup(dev, desc, sizeof(*of_desc), GFP_KERNEL);
+
+ if (!of_property_read_u32(dev->of_node, "bus-format", &val))
+ of_desc->bus_format = val;
+ if (!of_property_read_u32(dev->of_node, "delay,prepare", &val))
+ of_desc->delay.prepare = val;
+ if (!of_property_read_u32(dev->of_node, "delay,enable", &val))
+ of_desc->delay.enable = val;
+ if (!of_property_read_u32(dev->of_node, "delay,disable", &val))
+ of_desc->delay.disable = val;
+ if (!of_property_read_u32(dev->of_node, "delay,unprepare", &val))
+ of_desc->delay.unprepare = val;
+
panel->enabled = false;
panel->prepared = false;
- panel->desc = desc;
+ panel->desc = of_desc;
panel->dev = dev;
panel->supply = devm_regulator_get(dev, "power");
},
};
+static const struct drm_display_mode auo_b125han03_mode = {
+ .clock = 146900,
+ .hdisplay = 1920,
+ .hsync_start = 1920 + 48,
+ .hsync_end = 1920 + 48 + 32,
+ .htotal = 1920 + 48 + 32 + 140,
+ .vdisplay = 1080,
+ .vsync_start = 1080 + 2,
+ .vsync_end = 1080 + 2 + 5,
+ .vtotal = 1080 + 2 + 5 + 57,
+ .vrefresh = 60,
+ .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
+};
+
+static const struct panel_desc auo_b125han03 = {
+ .modes = &auo_b125han03_mode,
+ .num_modes = 1,
+ .bpc = 6,
+ .size = {
+ .width = 276,
+ .height = 156,
+ },
+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
+};
+
static const struct drm_display_mode auo_b133xtn01_mode = {
.clock = 69500,
.hdisplay = 1366,
},
};
+static const struct drm_display_mode boe_nv125fhm_n73_mode = {
+ .clock = 72300,
+ .hdisplay = 1366,
+ .hsync_start = 1366 + 80,
+ .hsync_end = 1366 + 80 + 20,
+ .htotal = 1366 + 80 + 20 + 60,
+ .vdisplay = 768,
+ .vsync_start = 768 + 12,
+ .vsync_end = 768 + 12 + 2,
+ .vtotal = 768 + 12 + 2 + 8,
+ .vrefresh = 60,
+ .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
+};
+
+static const struct panel_desc boe_nv125fhm_n73 = {
+ .modes = &boe_nv125fhm_n73_mode,
+ .num_modes = 1,
+ .bpc = 6,
+ .size = {
+ .width = 276,
+ .height = 156,
+ },
+ .delay = {
+ .unprepare = 160,
+ },
+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
+};
+
static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
.clock = 67000,
.hdisplay = 800,
},
};
+static const struct drm_display_mode innolux_n125hce_mode = {
+ .clock = 138780,
+ .hdisplay = 1920,
+ .hsync_start = 1920 + 80,
+ .hsync_end = 1920 + 80 + 30,
+ .htotal = 1920 + 80 + 30 + 50,
+ .vdisplay = 1080,
+ .vsync_start = 1080 + 12,
+ .vsync_end = 1080 + 12 + 4,
+ .vtotal = 1080 + 12 + 4 + 16,
+ .vrefresh = 60,
+ .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+};
+
+static const struct panel_desc innolux_n125hce = {
+ .modes = &innolux_n125hce_mode,
+ .num_modes = 1,
+ .bpc = 6,
+ .size = {
+ .width = 283,
+ .height = 168,
+ },
+ .delay = {
+ .unprepare = 600,
+ .enable = 100,
+ },
+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
+};
+
static const struct drm_display_mode innolux_n156bge_l21_mode = {
.clock = 69300,
.hdisplay = 1366,
.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
};
+static const struct drm_display_mode sharp_lcd_f402_mode = {
+ .clock = 205000,
+ .hdisplay = 1536,
+ .hsync_start = 1536 + 12,
+ .hsync_end = 1536 + 12 + 48,
+ .htotal = 1536 + 12 + 48 + 16,
+ .vdisplay = 2048,
+ .vsync_start = 2048 + 8,
+ .vsync_end = 2048 + 8 + 8,
+ .vtotal = 2048 + 8 + 8 + 4,
+ .vrefresh = 60,
+ .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
+};
+
+static const struct panel_desc sharp_lcd_f402 = {
+ .modes = &sharp_lcd_f402_mode,
+ .num_modes = 1,
+ .bpc = 8,
+ .size = {
+ .width = 95,
+ .height = 54,
+ },
+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
+};
+
static const struct drm_display_mode lg_lp079qx1_sp0v_mode = {
.clock = 200000,
.hdisplay = 1536,
.width = 129,
.height = 171,
},
+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
};
static const struct drm_display_mode lg_lp097qx1_spa1_mode = {
}, {
.compatible = "auo,b116xw03",
.data = &auo_b116xw03,
+ }, {
+ .compatible = "auo,b125han03",
+ .data = &auo_b125han03,
}, {
.compatible = "auo,b133htn01",
.data = &auo_b133htn01,
}, {
.compatible = "avic,tm070ddh03",
.data = &avic_tm070ddh03,
+ }, {
+ .compatible = "boe,nv125fhm-n73",
+ .data = &boe_nv125fhm_n73,
}, {
.compatible = "chunghwa,claa070wp03xg",
.data = &chunghwa_claa070wp03xg,
}, {
.compatible = "innolux,n116bge",
.data = &innolux_n116bge,
+ }, {
+ .compatible = "innolux,n125hce",
+ .data = &innolux_n125hce,
}, {
.compatible = "innolux,n156bge-l21",
.data = &innolux_n156bge_l21,
}, {
.compatible = "samsung,ltn140at29-301",
.data = &samsung_ltn140at29_301,
+ }, {
+ .compatible = "sharp,lcd-f402",
+ .data = &sharp_lcd_f402,
}, {
.compatible = "shelly,sca07010-bfn-lnn",
.data = &shelly_sca07010_bfn_lnn,