drm/radeon: use lower_32_bits where appropriate

[firefly-linux-kernel-4.4.55.git] / drivers / gpu / drm / radeon / r600.c

diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 6e887d004ebad7041e2080af850cc6ac2a12367d..c2ff17cebd91d38398abf0501e601e33fd5ae12d 100644 (file)
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -2724,7 +2724,7 @@ void r600_fence_ring_emit(struct radeon_device *rdev,
                /* EVENT_WRITE_EOP - flush caches, send int */
                radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
                radeon_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
-               radeon_ring_write(ring, addr & 0xffffffff);
+               radeon_ring_write(ring, lower_32_bits(addr));
                radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
                radeon_ring_write(ring, fence->seq);
                radeon_ring_write(ring, 0);
@@ -2763,7 +2763,7 @@ bool r600_semaphore_ring_emit(struct radeon_device *rdev,
                sel |= PACKET3_SEM_WAIT_ON_SIGNAL;
 
        radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
-       radeon_ring_write(ring, addr & 0xffffffff);
+       radeon_ring_write(ring, lower_32_bits(addr));
        radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | sel);
 
        return true;
@@ -2824,9 +2824,9 @@ int r600_copy_cpdma(struct radeon_device *rdev,
                if (size_in_bytes == 0)
                        tmp |= PACKET3_CP_DMA_CP_SYNC;
                radeon_ring_write(ring, PACKET3(PACKET3_CP_DMA, 4));
-               radeon_ring_write(ring, src_offset & 0xffffffff);
+               radeon_ring_write(ring, lower_32_bits(src_offset));
                radeon_ring_write(ring, tmp);
-               radeon_ring_write(ring, dst_offset & 0xffffffff);
+               radeon_ring_write(ring, lower_32_bits(dst_offset));
                radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
                radeon_ring_write(ring, cur_size_in_bytes);
                src_offset += cur_size_in_bytes;
@@ -2839,6 +2839,7 @@ int r600_copy_cpdma(struct radeon_device *rdev,
        r = radeon_fence_emit(rdev, fence, ring->idx);
        if (r) {
                radeon_ring_unlock_undo(rdev, ring);
+               radeon_semaphore_free(rdev, &sem, NULL);
                return r;
        }
 
@@ -3505,7 +3506,6 @@ int r600_irq_set(struct radeon_device *rdev)
        u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
        u32 grbm_int_cntl = 0;
        u32 hdmi0, hdmi1;
-       u32 d1grph = 0, d2grph = 0;
        u32 dma_cntl;
        u32 thermal_int = 0;
 
@@ -3614,8 +3614,8 @@ int r600_irq_set(struct radeon_device *rdev)
        WREG32(CP_INT_CNTL, cp_int_cntl);
        WREG32(DMA_CNTL, dma_cntl);
        WREG32(DxMODE_INT_MASK, mode_int);
-       WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
-       WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
+       WREG32(D1GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
+       WREG32(D2GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
        WREG32(GRBM_INT_CNTL, grbm_int_cntl);
        if (ASIC_IS_DCE3(rdev)) {
                WREG32(DC_HPD1_INT_CONTROL, hpd1);
@@ -3876,7 +3876,7 @@ restart_ih:
                                                wake_up(&rdev->irq.vblank_queue);
                                        }
                                        if (atomic_read(&rdev->irq.pflip[0]))
-                                               radeon_crtc_handle_flip(rdev, 0);
+                                               radeon_crtc_handle_vblank(rdev, 0);
                                        rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
                                        DRM_DEBUG("IH: D1 vblank\n");
                                }
@@ -3902,7 +3902,7 @@ restart_ih:
                                                wake_up(&rdev->irq.vblank_queue);
                                        }
                                        if (atomic_read(&rdev->irq.pflip[1]))
-                                               radeon_crtc_handle_flip(rdev, 1);
+                                               radeon_crtc_handle_vblank(rdev, 1);
                                        rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
                                        DRM_DEBUG("IH: D2 vblank\n");
                                }
@@ -3918,6 +3918,14 @@ restart_ih:
                                break;
                        }
                        break;
+               case 9: /* D1 pflip */
+                       DRM_DEBUG("IH: D1 flip\n");
+                       radeon_crtc_handle_flip(rdev, 0);
+                       break;
+               case 11: /* D2 pflip */
+                       DRM_DEBUG("IH: D2 flip\n");
+                       radeon_crtc_handle_flip(rdev, 1);
+                       break;
                case 19: /* HPD/DAC hotplug */
                        switch (src_data) {
                        case 0: