drm: add an fb creation ioctl that takes a pixel format v5

[firefly-linux-kernel-4.4.55.git] / drivers / gpu / drm / radeon / radeon_fb.c

diff --git a/drivers/gpu/drm/radeon/radeon_fb.c b/drivers/gpu/drm/radeon/radeon_fb.c
index 0b7b486c97e880e131fbde8afccec6a6a50538e1..ea110ad2a841793fb132d8acd2c45fff4e1e920c 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_fb.c
+++ b/drivers/gpu/drm/radeon/radeon_fb.c
@@ -103,7 +103,7 @@ static void radeonfb_destroy_pinned_object(struct drm_gem_object *gobj)
 }
 
 static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev,
-                                        struct drm_mode_fb_cmd *mode_cmd,
+                                        struct drm_mode_fb_cmd2 *mode_cmd,
                                         struct drm_gem_object **gobj_p)
 {
        struct radeon_device *rdev = rfbdev->rdev;
@@ -114,13 +114,17 @@ static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev,
        int ret;
        int aligned_size, size;
        int height = mode_cmd->height;
+       u32 bpp, depth;
+
+       drm_helper_get_fb_bpp_depth(mode_cmd->pixel_format, &depth, &bpp);
 
        /* need to align pitch with crtc limits */
-       mode_cmd->pitch = radeon_align_pitch(rdev, mode_cmd->width, mode_cmd->bpp, fb_tiled) * ((mode_cmd->bpp + 1) / 8);
+       mode_cmd->pitches[0] = radeon_align_pitch(rdev, mode_cmd->width, bpp,
+                                                 fb_tiled) * ((bpp + 1) / 8);
 
        if (rdev->family >= CHIP_R600)
                height = ALIGN(mode_cmd->height, 8);
-       size = mode_cmd->pitch * height;
+       size = mode_cmd->pitches[0] * height;
        aligned_size = ALIGN(size, PAGE_SIZE);
        ret = radeon_gem_object_create(rdev, aligned_size, 0,
                                       RADEON_GEM_DOMAIN_VRAM,
@@ -151,7 +155,7 @@ static int radeonfb_create_pinned_object(struct radeon_fbdev *rfbdev,
        if (tiling_flags) {
                ret = radeon_bo_set_tiling_flags(rbo,
                                                 tiling_flags | RADEON_TILING_SURFACE,
-                                                mode_cmd->pitch);
+                                                mode_cmd->pitches[0]);
                if (ret)
                        dev_err(rdev->dev, "FB failed to set tiling flags\n");
        }
@@ -187,7 +191,7 @@ static int radeonfb_create(struct radeon_fbdev *rfbdev,
        struct radeon_device *rdev = rfbdev->rdev;
        struct fb_info *info;
        struct drm_framebuffer *fb = NULL;
-       struct drm_mode_fb_cmd mode_cmd;
+       struct drm_mode_fb_cmd2 mode_cmd;
        struct drm_gem_object *gobj = NULL;
        struct radeon_bo *rbo = NULL;
        struct device *device = &rdev->pdev->dev;
@@ -201,8 +205,8 @@ static int radeonfb_create(struct radeon_fbdev *rfbdev,
        if ((sizes->surface_bpp == 24) && ASIC_IS_AVIVO(rdev))
                sizes->surface_bpp = 32;
 
-       mode_cmd.bpp = sizes->surface_bpp;
-       mode_cmd.depth = sizes->surface_depth;
+       mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp,
+                                                         sizes->surface_depth);
 
        ret = radeonfb_create_pinned_object(rfbdev, &mode_cmd, &gobj);
        rbo = gem_to_radeon_bo(gobj);