ARM64: DTS: Fix Firefly board audio driver

[firefly-linux-kernel-4.4.55.git] / drivers / gpu / drm / rockchip / dw-mipi-dsi.c

diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
index e6519cee2513a1e8648dd13dd4745f00bcdd1f46..0e948d6110419990b78146c40f112ce90954514d 100644 (file)
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
@@ -52,7 +52,17 @@
 
 /* disable turnrequest, turndisable, forcetxstopmode, forcerxmode */
 #define RK3399_GRF_SOC_CON22           0x6258
-#define RK3399_GRF_DSI_MODE            0xffff0000
+#define RK3399_GRF_DSI0_MODE           0xffff0000
+/* disable turndisable, forcetxstopmode, forcerxmode, enable */
+#define RK3399_GRF_SOC_CON23           0x625c
+#define RK3399_GRF_DSI1_MODE1          0xffff0000
+#define RK3399_GRF_DSI1_ENABLE         0x000f000f
+/* disable basedir and enable clk*/
+#define RK3399_GRF_SOC_CON24           0x6260
+#define RK3399_TXRX_MASTERSLAVEZ       BIT(7)
+#define RK3399_TXRX_ENABLECLK          BIT(6)
+#define RK3399_TXRX_BASEDIR            BIT(5)
+#define RK3399_GRF_DSI1_MODE2          0x00600040
 
 #define DSI_VERSION                    0x00
 #define DSI_PWR_UP                     0x04
@@ -295,8 +305,12 @@ struct dw_mipi_dsi_plat_data {
        u32 grf_switch_reg;
        u32 grf_dsi0_mode;
        u32 grf_dsi0_mode_reg;
+       u32 grf_dsi1_mode;
+       u32 grf_dsi1_mode_reg1;
        u32 dsi1_basedir;
        u32 dsi1_masterslavez;
+       u32 dsi1_enableclk;
+       u32 grf_dsi1_mode_reg2;
        u32 grf_dsi1_cfg_reg;
        unsigned int max_data_lanes;
        u32 max_bit_rate_per_lane;
@@ -409,7 +423,7 @@ static int rockchip_wait_w_pld_fifo_not_full(struct dw_mipi_dsi *dsi)
        u32 sts;
        int ret;
 
-       ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
+       ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
                                 sts, !(sts & GEN_PLD_W_FULL), 10,
                                 CMD_PKT_STATUS_TIMEOUT_US);
        if (ret < 0) {
@@ -425,7 +439,7 @@ static int rockchip_wait_cmd_fifo_not_full(struct dw_mipi_dsi *dsi)
        u32 sts;
        int ret;
 
-       ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
+       ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
                                 sts, !(sts & GEN_CMD_FULL), 10,
                                 CMD_PKT_STATUS_TIMEOUT_US);
        if (ret < 0) {
@@ -443,7 +457,7 @@ static int rockchip_wait_write_fifo_empty(struct dw_mipi_dsi *dsi)
        int ret;
 
        mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
-       ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
+       ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
                                 sts, (sts & mask) == mask, 10,
                                 CMD_PKT_STATUS_TIMEOUT_US);
        if (ret < 0) {
@@ -538,14 +552,14 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi)
        dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
                                     PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
 
-       ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS,
+       ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
                                 val, val & LOCK, 1000, PHY_STATUS_TIMEOUT_US);
        if (ret < 0) {
                dev_err(dsi->dev, "failed to wait for phy lock state\n");
                goto phy_init_end;
        }
 
-       ret = readx_poll_timeout(readl, dsi->base + DSI_PHY_STATUS,
+       ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
                                 val, val & STOP_STATE_CLK_LANE, 1000,
                                 PHY_STATUS_TIMEOUT_US);
        if (ret < 0)
@@ -661,6 +675,9 @@ static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
        struct dw_mipi_dsi *dsi = host_to_dsi(host);
        int lanes;
 
+       if (dsi->master)
+               return 0;
+
        lanes = dsi->slave ? device->lanes / 2 : device->lanes;
 
        if (lanes > dsi->pdata->max_data_lanes) {
@@ -686,6 +703,12 @@ static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
                dsi->slave->mode_flags = device->mode_flags;
        }
 
+       dsi->panel = of_drm_find_panel(device->dev.of_node);
+       if (!dsi->panel) {
+               DRM_ERROR("failed to find panel\n");
+               return -ENODEV;
+       }
+
        return 0;
 }
 
@@ -809,10 +832,14 @@ static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
                                 enum dw_mipi_dsi_mode mode)
 {
-       if (mode == DSI_COMMAND_MODE)
+       if (mode == DSI_COMMAND_MODE) {
                dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
-       else
+       } else {
+               dsi_write(dsi, DSI_PWR_UP, RESET);
+               dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
                dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
+               dsi_write(dsi, DSI_PWR_UP, POWERUP);
+       }
 }
 
 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
@@ -1046,6 +1073,19 @@ static void rockchip_dsi_grf_config(struct dw_mipi_dsi *dsi, int vop_id)
                      (pdata->dsi1_masterslavez << 16) |
                      (pdata->dsi1_basedir << 16);
                regmap_write(dsi->grf_regmap, pdata->grf_dsi1_cfg_reg, val);
+
+               if (pdata->grf_dsi0_mode_reg)
+                       regmap_write(dsi->grf_regmap, pdata->grf_dsi0_mode_reg,
+                                    pdata->grf_dsi0_mode);
+               if (pdata->grf_dsi1_mode_reg1)
+                       regmap_write(dsi->grf_regmap, pdata->grf_dsi1_mode_reg1,
+                                    pdata->grf_dsi1_mode);
+               if (pdata->grf_dsi1_mode_reg2)
+                       regmap_write(dsi->grf_regmap, pdata->grf_dsi1_mode_reg2,
+                                    RK3399_GRF_DSI1_MODE2);
+               if (pdata->grf_dsi1_mode_reg1)
+                       regmap_write(dsi->grf_regmap, pdata->grf_dsi1_mode_reg1,
+                                    RK3399_GRF_DSI1_ENABLE);
        } else {
                if (vop_id)
                        val = pdata->dsi0_en_bit |
@@ -1054,6 +1094,7 @@ static void rockchip_dsi_grf_config(struct dw_mipi_dsi *dsi, int vop_id)
                        val = pdata->dsi0_en_bit << 16;
 
                regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
+
        }
 
        dev_info(dsi->dev, "vop %s output to dsi0\n", (vop_id) ? "LIT" : "BIG");
@@ -1071,6 +1112,13 @@ static void rockchip_dsi_pre_init(struct dw_mipi_dsi *dsi)
                return;
        }
 
+       if (dsi->dphy.phy) {
+               rockchip_dsi_set_hs_clk(dsi);
+               phy_power_on(dsi->dphy.phy);
+       } else {
+               dw_mipi_dsi_get_lane_bps(dsi);
+       }
+
        pm_runtime_get_sync(dsi->dev);
 
        if (dsi->rst) {
@@ -1081,19 +1129,14 @@ static void rockchip_dsi_pre_init(struct dw_mipi_dsi *dsi)
                udelay(10);
        }
 
-       if (dsi->dphy.phy) {
-               rockchip_dsi_set_hs_clk(dsi);
-               phy_power_on(dsi->dphy.phy);
-       } else {
-               dw_mipi_dsi_get_lane_bps(dsi);
-       }
-
        dev_info(dsi->dev, "final DSI-Link bandwidth: %u x %d Mbps\n",
                 dsi->lane_mbps, dsi->lanes);
 }
 
 static void rockchip_dsi_host_init(struct dw_mipi_dsi *dsi)
 {
+       const struct dw_mipi_dsi_plat_data *pdata = dsi->pdata;
+
        dw_mipi_dsi_init(dsi);
        dw_mipi_dsi_dpi_config(dsi, &dsi->mode);
        dw_mipi_dsi_packet_handler_config(dsi);
@@ -1106,6 +1149,12 @@ static void rockchip_dsi_host_init(struct dw_mipi_dsi *dsi)
        dw_mipi_dsi_dphy_timing_config(dsi);
        dw_mipi_dsi_dphy_interface_config(dsi);
        dw_mipi_dsi_clear_err(dsi);
+
+               if (pdata->grf_dsi0_mode_reg)
+                       regmap_write(dsi->grf_regmap, pdata->grf_dsi0_mode_reg,
+                                    pdata->grf_dsi0_mode);
+
+
 }
 
 static void rockchip_dsi_init(struct dw_mipi_dsi *dsi)
@@ -1120,7 +1169,6 @@ static void rockchip_dsi_init(struct dw_mipi_dsi *dsi)
 
 static void rockchip_dsi_enable(struct dw_mipi_dsi *dsi)
 {
-       dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
        dw_mipi_dsi_set_mode(dsi, DSI_VIDEO_MODE);
        clk_disable_unprepare(dsi->dphy.ref_clk);
        clk_disable_unprepare(dsi->pclk);
@@ -1136,7 +1184,6 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
 
        vop_id = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder);
 
-       rockchip_dsi_grf_config(dsi, vop_id);
        rockchip_dsi_init(dsi);
 
        if (dsi->panel)
@@ -1146,6 +1193,8 @@ static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
 
        if (dsi->panel)
                drm_panel_enable(dsi->panel);
+
+       rockchip_dsi_grf_config(dsi, vop_id);
 }
 
 static int
@@ -1361,8 +1410,14 @@ static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = {
        .dsi0_en_bit = RK3399_DSI0_SEL_VOP_LIT,
        .dsi1_en_bit = RK3399_DSI1_SEL_VOP_LIT,
        .grf_switch_reg = RK3399_GRF_SOC_CON19,
-       .grf_dsi0_mode = RK3399_GRF_DSI_MODE,
+       .grf_dsi0_mode = RK3399_GRF_DSI0_MODE,
        .grf_dsi0_mode_reg = RK3399_GRF_SOC_CON22,
+       .grf_dsi1_mode = RK3399_GRF_DSI1_MODE1,
+       .grf_dsi1_mode_reg1 = RK3399_GRF_SOC_CON23,
+       .dsi1_basedir = RK3399_TXRX_BASEDIR,
+       .dsi1_masterslavez = RK3399_TXRX_MASTERSLAVEZ,
+       .dsi1_enableclk = RK3399_TXRX_ENABLECLK,
+       .grf_dsi1_mode_reg2 = RK3399_GRF_SOC_CON24,
        .max_data_lanes = 4,
        .max_bit_rate_per_lane = 1500000000,
        .has_vop_sel = true,
@@ -1400,7 +1455,6 @@ static int dw_mipi_dsi_bind(struct device *dev, struct device *master,
        if (dsi->master)
                return 0;
 
-       dsi->panel = of_drm_find_panel(dsi->panel_node);
        if (!dsi->panel)
                return -EPROBE_DEFER;
 
@@ -1434,26 +1488,6 @@ static const struct component_ops dw_mipi_dsi_ops = {
        .unbind = dw_mipi_dsi_unbind,
 };
 
-static int rockchip_dsi_parse_dt(struct dw_mipi_dsi *dsi)
-{
-       struct device_node *np = dsi->dev->of_node;
-       struct device_node *endpoint, *remote = NULL;
-
-       endpoint = of_graph_get_endpoint_by_regs(np, 1, -1);
-       if (endpoint) {
-               remote = of_graph_get_remote_port_parent(endpoint);
-               of_node_put(endpoint);
-               if (!remote) {
-                       dev_err(dsi->dev, "No panel/bridge connected\n");
-                       return -ENODEV;
-               }
-       }
-
-       dsi->panel_node = remote;
-
-       return 0;
-}
-
 static int rockchip_dsi_get_reset_handle(struct dw_mipi_dsi *dsi)
 {
        struct device *dev = dsi->dev;
@@ -1580,7 +1614,6 @@ static int dw_mipi_dsi_probe(struct platform_device *pdev)
        dsi->dev = dev;
        dsi->pdata = pdata;
 
-       rockchip_dsi_parse_dt(dsi);
        rockchip_dsi_ioremap_resource(pdev, dsi);
        rockchip_dsi_clk_get(dsi);
        rockchip_dsi_dphy_parse(dsi);