#include <linux/math64.h>
#include <linux/module.h>
#include <linux/of_device.h>
+#include <linux/phy/phy.h>
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
+#include <linux/reset.h>
#include <linux/mfd/syscon.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>
u32 grf_dsi0_mode;
u32 grf_dsi0_mode_reg;
unsigned int max_data_lanes;
+ u32 max_bit_rate_per_lane;
+ bool has_vop_sel;
enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
struct drm_display_mode *mode);
};
struct drm_encoder encoder;
struct drm_connector connector;
struct mipi_dsi_host dsi_host;
+ struct phy *phy;
struct drm_panel *panel;
struct device *dev;
struct regmap *grf_regmap;
+ struct reset_control *rst;
void __iomem *base;
struct clk *pllref_clk;
struct clk *pclk;
struct clk *phy_cfg_clk;
- int dpms_mode;
unsigned int lane_mbps; /* per lane */
u32 channel;
u32 lanes;
u32 format;
u16 input_div;
u16 feedback_div;
- struct drm_display_mode *mode;
+ struct drm_display_mode mode;
const struct dw_mipi_dsi_plat_data *pdata;
};
{
int refresh, two_frames;
- refresh = drm_mode_vrefresh(dsi->mode);
+ refresh = drm_mode_vrefresh(&dsi->mode);
two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2;
msleep(two_frames);
}
return bpp;
}
- mpclk = DIV_ROUND_UP(dsi->mode->clock, MSEC_PER_SEC);
+ mpclk = DIV_ROUND_UP(dsi->mode.clock, MSEC_PER_SEC);
if (mpclk) {
/* take 1 / 0.9, since mbps must big than bandwidth of RGB */
tmp = mpclk * (bpp / dsi->lanes) * 10 / 9;
return -EINVAL;
}
- if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) ||
- !(device->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)) {
+ if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)) {
dev_err(dsi->dev, "device mode is unsupported\n");
return -EINVAL;
}
lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
- frac = lbcc % dsi->mode->clock;
- lbcc = lbcc / dsi->mode->clock;
+ frac = lbcc % dsi->mode.clock;
+ lbcc = lbcc / dsi->mode.clock;
if (frac)
lbcc++;
static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi)
{
u32 htotal, hsa, hbp, lbcc;
- struct drm_display_mode *mode = dsi->mode;
+ struct drm_display_mode *mode = &dsi->mode;
htotal = mode->htotal;
hsa = mode->hsync_end - mode->hsync_start;
static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi)
{
u32 vactive, vsa, vfp, vbp;
- struct drm_display_mode *mode = dsi->mode;
+ struct drm_display_mode *mode = &dsi->mode;
vactive = mode->vdisplay;
vsa = mode->vsync_end - mode->vsync_start;
static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
{
- dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40)
- | PHY_LP2HS_TIME(0x40) | MAX_RD_TIME(10000));
+ dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x14)
+ | PHY_LP2HS_TIME(0x10) | MAX_RD_TIME(10000));
dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40)
| PHY_CLKLP2HS_TIME(0x40));
struct drm_display_mode *adjusted_mode)
{
struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
- int ret;
-
- if (dsi->dpms_mode == DRM_MODE_DPMS_ON)
- return;
-
- dsi->mode = adjusted_mode;
-
- ret = dw_mipi_dsi_get_lane_bps(dsi);
- if (ret < 0)
- return;
-
- if (clk_prepare_enable(dsi->pclk)) {
- dev_err(dsi->dev, "%s: Failed to enable pclk\n", __func__);
- return;
- }
-
- pm_runtime_get_sync(dsi->dev);
-
- dw_mipi_dsi_init(dsi);
- dw_mipi_dsi_dpi_config(dsi, mode);
- dw_mipi_dsi_packet_handler_config(dsi);
- dw_mipi_dsi_video_mode_config(dsi);
- dw_mipi_dsi_video_packet_config(dsi, mode);
- dw_mipi_dsi_command_mode_config(dsi);
- dw_mipi_dsi_line_timer_config(dsi);
- dw_mipi_dsi_vertical_timing_config(dsi);
- dw_mipi_dsi_dphy_timing_config(dsi);
- dw_mipi_dsi_dphy_interface_config(dsi);
- dw_mipi_dsi_clear_err(dsi);
- if (drm_panel_prepare(dsi->panel))
- dev_err(dsi->dev, "failed to prepare panel\n");
- clk_disable_unprepare(dsi->pclk);
+ drm_mode_copy(&dsi->mode, adjusted_mode);
}
static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
{
struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
- if (dsi->dpms_mode != DRM_MODE_DPMS_ON)
- return;
-
drm_panel_disable(dsi->panel);
if (clk_prepare_enable(dsi->pclk)) {
dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE);
dw_mipi_dsi_disable(dsi);
+ phy_power_off(dsi->phy);
pm_runtime_put(dsi->dev);
clk_disable_unprepare(dsi->pclk);
- dsi->dpms_mode = DRM_MODE_DPMS_OFF;
}
static bool dw_mipi_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
return true;
}
-static void dw_mipi_dsi_encoder_commit(struct drm_encoder *encoder)
+static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
{
struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder);
const struct dw_mipi_dsi_plat_data *pdata = dsi->pdata;
int mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder);
+ int ret;
u32 val;
if (clk_prepare_enable(dsi->pclk)) {
return;
}
+ if (dsi->rst) {
+ /* MIPI DSI APB software reset request. */
+ reset_control_assert(dsi->rst);
+ udelay(10);
+ reset_control_deassert(dsi->rst);
+ udelay(10);
+ }
+
+ pm_runtime_get_sync(dsi->dev);
+
+ phy_power_on(dsi->phy);
+
+ if (dsi->phy) {
+ /*
+ * If using the third party PHY, we get the lane
+ * rate information from PHY.
+ */
+ dsi->lane_mbps = phy_get_bus_width(dsi->phy);
+ } else {
+ ret = dw_mipi_dsi_get_lane_bps(dsi);
+ if (ret < 0)
+ return;
+ }
+
+ dw_mipi_dsi_init(dsi);
+ dw_mipi_dsi_dpi_config(dsi, &dsi->mode);
+ dw_mipi_dsi_packet_handler_config(dsi);
+ dw_mipi_dsi_video_mode_config(dsi);
+ dw_mipi_dsi_video_packet_config(dsi, &dsi->mode);
+ dw_mipi_dsi_command_mode_config(dsi);
+ dw_mipi_dsi_line_timer_config(dsi);
+ dw_mipi_dsi_vertical_timing_config(dsi);
+ dw_mipi_dsi_dphy_timing_config(dsi);
+ dw_mipi_dsi_dphy_interface_config(dsi);
+ dw_mipi_dsi_clear_err(dsi);
+ if (drm_panel_prepare(dsi->panel))
+ dev_err(dsi->dev, "failed to prepare panel\n");
+
if (pdata->grf_dsi0_mode_reg)
regmap_write(dsi->grf_regmap, pdata->grf_dsi0_mode_reg,
pdata->grf_dsi0_mode);
- dw_mipi_dsi_phy_init(dsi);
+ if (!dsi->phy)
+ dw_mipi_dsi_phy_init(dsi);
+
dw_mipi_dsi_wait_for_two_frames(dsi);
dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE);
clk_disable_unprepare(dsi->pclk);
+ if (!pdata->has_vop_sel)
+ return;
+
if (mux)
val = pdata->dsi0_en_bit | (pdata->dsi0_en_bit << 16);
else
regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val);
dev_dbg(dsi->dev, "vop %s output to dsi0\n", (mux) ? "LIT" : "BIG");
- dsi->dpms_mode = DRM_MODE_DPMS_ON;
}
static int
static struct drm_encoder_helper_funcs
dw_mipi_dsi_encoder_helper_funcs = {
.mode_fixup = dw_mipi_dsi_encoder_mode_fixup,
- .commit = dw_mipi_dsi_encoder_commit,
.mode_set = dw_mipi_dsi_encoder_mode_set,
+ .enable = dw_mipi_dsi_encoder_enable,
.disable = dw_mipi_dsi_encoder_disable,
.atomic_check = dw_mipi_dsi_encoder_atomic_check,
};
return &dsi->encoder;
}
+static int dw_mipi_loader_protect(struct drm_connector *connector, bool on)
+{
+ struct dw_mipi_dsi *dsi = con_to_dsi(connector);
+
+ if (on)
+ pm_runtime_get_sync(dsi->dev);
+ else
+ pm_runtime_put(dsi->dev);
+
+ return 0;
+}
+
static struct drm_connector_helper_funcs dw_mipi_dsi_connector_helper_funcs = {
+ .loader_protect = dw_mipi_loader_protect,
.get_modes = dw_mipi_dsi_connector_get_modes,
.mode_valid = dw_mipi_dsi_mode_valid,
.best_encoder = dw_mipi_dsi_connector_best_encoder,
.dsi1_en_bit = RK3288_DSI1_SEL_VOP_LIT,
.grf_switch_reg = RK3288_GRF_SOC_CON6,
.max_data_lanes = 4,
+ .max_bit_rate_per_lane = 1500000000,
+ .has_vop_sel = true,
};
static struct dw_mipi_dsi_plat_data rk3399_mipi_dsi_drv_data = {
.grf_dsi0_mode = RK3399_GRF_DSI_MODE,
.grf_dsi0_mode_reg = RK3399_GRF_SOC_CON22,
.max_data_lanes = 4,
+ .max_bit_rate_per_lane = 1500000000,
+ .has_vop_sel = true,
+};
+
+static struct dw_mipi_dsi_plat_data rk3368_mipi_dsi_drv_data = {
+ .max_data_lanes = 4,
+ .max_bit_rate_per_lane = 1000000000,
};
static const struct of_device_id dw_mipi_dsi_dt_ids[] = {
},{
.compatible = "rockchip,rk3399-mipi-dsi",
.data = &rk3399_mipi_dsi_drv_data,
+ }, {
+ .compatible = "rockchip,rk3368-mipi-dsi",
+ .data = &rk3368_mipi_dsi_drv_data,
},
{ /* sentinel */ }
};
struct resource *res;
int ret;
- dsi->dpms_mode = DRM_MODE_DPMS_OFF;
-
if (!dsi->panel)
return -EPROBE_DEFER;
if (ret)
return ret;
+ dsi->phy = devm_phy_optional_get(dev, "mipi_dphy");
+ if (IS_ERR(dsi->phy)) {
+ ret = PTR_ERR(dsi->phy);
+ dev_err(dev, "failed to get mipi dphy: %d\n", ret);
+ return ret;
+ }
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
return -ENODEV;
if (IS_ERR(dsi->base))
return PTR_ERR(dsi->base);
- dsi->pllref_clk = devm_clk_get(dev, "ref");
- if (IS_ERR(dsi->pllref_clk)) {
- ret = PTR_ERR(dsi->pllref_clk);
- dev_err(dev, "Unable to get pll reference clock: %d\n", ret);
- return ret;
- }
-
dsi->pclk = devm_clk_get(dev, "pclk");
if (IS_ERR(dsi->pclk)) {
ret = PTR_ERR(dsi->pclk);
return ret;
}
+ /* optional */
+ dsi->pllref_clk = devm_clk_get(dev, "ref");
+ if (IS_ERR(dsi->pllref_clk)) {
+ dev_info(dev, "No PHY reference clock specified\n");
+ dsi->pllref_clk = NULL;
+ }
+
+ /* optional */
dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg");
- if (IS_ERR(dsi->phy_cfg_clk))
- dev_dbg(dev, "have not phy_cfg_clk\n");
+ if (IS_ERR(dsi->phy_cfg_clk)) {
+ dev_info(dev, "No PHY APB clock specified\n");
+ dsi->phy_cfg_clk = NULL;
+ }
ret = clk_prepare_enable(dsi->pllref_clk);
if (ret) {
return ret;
}
+ dsi->rst = devm_reset_control_get_optional(dev, "apb");
+ if (IS_ERR(dsi->rst)) {
+ dev_info(dev, "no reset control specified\n");
+ dsi->rst = NULL;
+ }
+
ret = dw_mipi_dsi_register(drm, dsi);
if (ret) {
dev_err(dev, "Failed to register mipi_dsi: %d\n", ret);
projects / firefly-linux-kernel-4.4.55.git / blobdiff