#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
+#include <linux/pm_runtime.h>
#include <drm/drm_of.h>
#include <drm/drmP.h>
#define to_rockchip_hdmi(x) container_of(x, struct rockchip_hdmi, x)
-#define CLK_SLOP(clk) ((clk) / 1000)
-#define CLK_PLUS_SLOP(clk) ((clk) + CLK_SLOP(clk))
-
-static const int dw_hdmi_rates[] = {
- 25176471, /* for 25.175 MHz, 0.006% off */
- 25200000,
- 27000000,
- 28320000,
- 30240000,
- 31500000,
- 32000000,
- 33750000,
- 36000000,
- 40000000,
- 49500000,
- 50000000,
- 54000000,
- 57290323, /* for 57.284 MHz, .011 % off */
- 65000000,
- 68250000,
- 71000000,
- 72000000,
- 73250000,
- 74250000,
- 74437500, /* for 74.44 MHz, .003% off */
- 75000000,
- 78750000,
- 78800000,
- 79500000,
- 83500000,
- 85500000,
- 88750000,
- 97750000,
- 101000000,
- 106500000,
- 108000000,
- 115500000,
- 118666667, /* for 118.68 MHz, .011% off */
- 119000000,
- 121714286, /* for 121.75 MHz, .029% off */
- 135000000,
- 136800000, /* for 136.75 MHz, .037% off */
- 146250000,
- 148500000,
- 154000000,
- 162000000,
- 297000000,
+/*
+ * There are some rates that would be ranged for better clock jitter at
+ * Chrome OS tree, like 25.175Mhz would range to 25.170732Mhz. But due
+ * to the clock is aglined to KHz in struct drm_display_mode, this would
+ * bring some inaccurate error if we still run the compute_n math, so
+ * let's just code an const table for it until we can actually get the
+ * right clock rate.
+ */
+static const struct dw_hdmi_audio_tmds_n rockchip_werid_tmds_n_table[] = {
+ /* 25176471 for 25.175 MHz = 428000000 / 17. */
+ { .tmds = 25177000, .n_32k = 4352, .n_44k1 = 14994, .n_48k = 6528, },
+ /* 57290323 for 57.284 MHz */
+ { .tmds = 57291000, .n_32k = 3968, .n_44k1 = 4557, .n_48k = 5952, },
+ /* 74437500 for 74.44 MHz = 297750000 / 4 */
+ { .tmds = 74438000, .n_32k = 8192, .n_44k1 = 18816, .n_48k = 4096, },
+ /* 118666667 for 118.68 MHz */
+ { .tmds = 118667000, .n_32k = 4224, .n_44k1 = 5292, .n_48k = 6336, },
+ /* 121714286 for 121.75 MHz */
+ { .tmds = 121715000, .n_32k = 4480, .n_44k1 = 6174, .n_48k = 6272, },
+ /* 136800000 for 136.75 MHz */
+ { .tmds = 136800000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
+ /* End of table */
+ { .tmds = 0, .n_32k = 0, .n_44k1 = 0, .n_48k = 0, },
};
static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
{ 74250000, 0x8009, 0x0004, 0x0272},
{ 165000000, 0x802b, 0x0004, 0x0209},
{ 297000000, 0x8039, 0x0005, 0x028d},
+ { 594000000, 0x8039, 0x0000, 0x019d},
{ ~0UL, 0x0000, 0x0000, 0x0000}
};
dw_hdmi_rockchip_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
{
- int pclk = mode->clock * 1000;
- int num_rates = ARRAY_SIZE(dw_hdmi_rates);
- int i;
+ struct drm_encoder *encoder = connector->encoder;
+ enum drm_mode_status status = MODE_OK;
+ struct drm_device *dev = connector->dev;
+ struct rockchip_drm_private *priv = dev->dev_private;
+ struct drm_crtc *crtc;
/*
* Pixel clocks we support are always < 2GHz and so fit in an
if (mode->clock > INT_MAX / 1000)
return MODE_BAD;
- for (i = 0; i < num_rates; i++) {
- int slop = CLK_SLOP(pclk);
+ if (!encoder) {
+ const struct drm_connector_helper_funcs *funcs;
+
+ funcs = connector->helper_private;
+ if (funcs->atomic_best_encoder)
+ encoder = funcs->atomic_best_encoder(connector,
+ connector->state);
+ else
+ encoder = funcs->best_encoder(connector);
+ }
- if ((pclk >= dw_hdmi_rates[i] - slop) &&
- (pclk <= dw_hdmi_rates[i] + slop))
- return MODE_OK;
+ if (!encoder || !encoder->possible_crtcs)
+ return MODE_BAD;
+ /*
+ * ensure all drm display mode can work, if someone want support more
+ * resolutions, please limit the possible_crtc, only connect to
+ * needed crtc.
+ */
+ drm_for_each_crtc(crtc, connector->dev) {
+ int pipe = drm_crtc_index(crtc);
+ const struct rockchip_crtc_funcs *funcs =
+ priv->crtc_funcs[pipe];
+
+ if (!(encoder->possible_crtcs & drm_crtc_mask(crtc)))
+ continue;
+ if (!funcs || !funcs->mode_valid)
+ continue;
+
+ status = funcs->mode_valid(crtc, mode,
+ DRM_MODE_CONNECTOR_HDMIA);
+ if (status != MODE_OK)
+ return status;
}
- return MODE_BAD;
+ return status;
}
static const struct drm_encoder_funcs dw_hdmi_rockchip_encoder_funcs = {
{
}
-static bool
-dw_hdmi_rockchip_encoder_mode_fixup(struct drm_encoder *encoder,
- const struct drm_display_mode *mode,
- struct drm_display_mode *adj_mode)
-{
- return true;
-}
-
-static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder,
- struct drm_display_mode *mode,
- struct drm_display_mode *adj_mode)
-{
- struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
-
- clk_set_rate(hdmi->vpll_clk, adj_mode->clock * 1000);
-}
-
static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder)
{
struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
+ struct drm_crtc *crtc = encoder->crtc;
u32 lcdsel_grf_reg, lcdsel_mask;
u32 val;
int mux;
int ret;
+ if (WARN_ON(!crtc || !crtc->state))
+ return;
+
+ clk_set_rate(hdmi->vpll_clk,
+ crtc->state->adjusted_mode.crtc_clock * 1000);
+
switch (hdmi->dev_type) {
case RK3288_HDMI:
lcdsel_grf_reg = RK3288_GRF_SOC_CON6;
{
struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
- s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
+ if (crtc_state->mode.flags & DRM_MODE_FLAG_420_MASK) {
+ s->output_mode = ROCKCHIP_OUT_MODE_YUV420;
+ s->bus_format = MEDIA_BUS_FMT_YUV8_1X24;
+ } else {
+ s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
+ s->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
+ }
s->output_type = DRM_MODE_CONNECTOR_HDMIA;
return 0;
}
static const struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
- .mode_fixup = dw_hdmi_rockchip_encoder_mode_fixup,
- .mode_set = dw_hdmi_rockchip_encoder_mode_set,
.enable = dw_hdmi_rockchip_encoder_enable,
.disable = dw_hdmi_rockchip_encoder_disable,
.atomic_check = dw_hdmi_rockchip_encoder_atomic_check,
.cur_ctr = rockchip_cur_ctr,
.phy_config = rockchip_phy_config,
.dev_type = RK3288_HDMI,
+ .tmds_n_table = rockchip_werid_tmds_n_table,
};
static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
static int dw_hdmi_rockchip_probe(struct platform_device *pdev)
{
+ pm_runtime_enable(&pdev->dev);
+ pm_runtime_get_sync(&pdev->dev);
+
return component_add(&pdev->dev, &dw_hdmi_rockchip_ops);
}
static int dw_hdmi_rockchip_remove(struct platform_device *pdev)
{
component_del(&pdev->dev, &dw_hdmi_rockchip_ops);
+ pm_runtime_disable(&pdev->dev);
return 0;
}
+static int dw_hdmi_rockchip_suspend(struct device *dev)
+{
+ dw_hdmi_suspend(dev);
+ pm_runtime_put_sync(dev);
+
+ return 0;
+}
+
+static int dw_hdmi_rockchip_resume(struct device *dev)
+{
+ pm_runtime_get_sync(dev);
+ dw_hdmi_resume(dev);
+
+ return 0;
+}
+
+static const struct dev_pm_ops dw_hdmi_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(dw_hdmi_rockchip_suspend,
+ dw_hdmi_rockchip_resume)
+};
+
static struct platform_driver dw_hdmi_rockchip_pltfm_driver = {
.probe = dw_hdmi_rockchip_probe,
.remove = dw_hdmi_rockchip_remove,
.driver = {
.name = "dwhdmi-rockchip",
.of_match_table = dw_hdmi_rockchip_dt_ids,
+ .pm = &dw_hdmi_pm_ops,
},
};
projects / firefly-linux-kernel-4.4.55.git / blobdiff