#include <drm/drm.h>
#include <drm/drmP.h>
+#include <drm/drm_atomic.h>
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
+#include <drm/drm_flip_work.h>
#include <drm/drm_plane_helper.h>
+#include <linux/devfreq.h>
+#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
+#include <linux/iopoll.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
#include <linux/delay.h>
+#include <linux/sort.h>
+#include <uapi/drm/rockchip_drm.h>
#include "rockchip_drm_drv.h"
#include "rockchip_drm_gem.h"
#include "rockchip_drm_fb.h"
#include "rockchip_drm_vop.h"
+#include "rockchip_drm_backlight.h"
-#define VOP_REG(off, _mask, s) \
- {.offset = off, \
- .mask = _mask, \
- .shift = s,}
+#define VOP_REG_SUPPORT(vop, reg) \
+ (!reg.major || (reg.major == VOP_MAJOR(vop->data->version) && \
+ reg.begin_minor <= VOP_MINOR(vop->data->version) && \
+ reg.end_minor >= VOP_MINOR(vop->data->version) && \
+ reg.mask))
-#define __REG_SET_RELAXED(x, off, mask, shift, v) \
- vop_mask_write_relaxed(x, off, (mask) << shift, (v) << shift)
-#define __REG_SET_NORMAL(x, off, mask, shift, v) \
- vop_mask_write(x, off, (mask) << shift, (v) << shift)
+#define VOP_WIN_SUPPORT(vop, win, name) \
+ VOP_REG_SUPPORT(vop, win->phy->name)
-#define REG_SET(x, base, reg, v, mode) \
- __REG_SET_##mode(x, base + reg.offset, reg.mask, reg.shift, v)
+#define VOP_CTRL_SUPPORT(vop, name) \
+ VOP_REG_SUPPORT(vop, vop->data->ctrl->name)
+
+#define VOP_INTR_SUPPORT(vop, name) \
+ VOP_REG_SUPPORT(vop, vop->data->intr->name)
+
+#define __REG_SET(x, off, mask, shift, v, write_mask, relaxed) \
+ vop_mask_write(x, off, mask, shift, v, write_mask, relaxed)
+
+#define _REG_SET(vop, name, off, reg, mask, v, relaxed) \
+ do { \
+ if (VOP_REG_SUPPORT(vop, reg)) \
+ __REG_SET(vop, off + reg.offset, mask, reg.shift, \
+ v, reg.write_mask, relaxed); \
+ else \
+ dev_dbg(vop->dev, "Warning: not support "#name"\n"); \
+ } while(0)
+
+#define REG_SET(x, name, off, reg, v, relaxed) \
+ _REG_SET(x, name, off, reg, reg.mask, v, relaxed)
+#define REG_SET_MASK(x, name, off, reg, mask, v, relaxed) \
+ _REG_SET(x, name, off, reg, reg.mask & mask, v, relaxed)
#define VOP_WIN_SET(x, win, name, v) \
- REG_SET(x, win->base, win->phy->name, v, RELAXED)
+ REG_SET(x, name, win->offset, VOP_WIN_NAME(win, name), v, true)
+#define VOP_WIN_SET_EXT(x, win, ext, name, v) \
+ REG_SET(x, name, 0, win->ext->name, v, true)
#define VOP_SCL_SET(x, win, name, v) \
- REG_SET(x, win->base, win->phy->scl->name, v, RELAXED)
+ REG_SET(x, name, win->offset, win->phy->scl->name, v, true)
+#define VOP_SCL_SET_EXT(x, win, name, v) \
+ REG_SET(x, name, win->offset, win->phy->scl->ext->name, v, true)
+
#define VOP_CTRL_SET(x, name, v) \
- REG_SET(x, 0, (x)->data->ctrl->name, v, NORMAL)
+ REG_SET(x, name, 0, (x)->data->ctrl->name, v, false)
+
+#define VOP_INTR_GET(vop, name) \
+ vop_read_reg(vop, 0, &vop->data->ctrl->name)
+
+#define VOP_INTR_SET(vop, name, v) \
+ REG_SET(vop, name, 0, vop->data->intr->name, \
+ v, false)
+#define VOP_INTR_SET_MASK(vop, name, mask, v) \
+ REG_SET_MASK(vop, name, 0, vop->data->intr->name, \
+ mask, v, false)
+
+#define VOP_INTR_SET_TYPE(vop, name, type, v) \
+ do { \
+ int i, reg = 0, mask = 0; \
+ for (i = 0; i < vop->data->intr->nintrs; i++) { \
+ if (vop->data->intr->intrs[i] & type) { \
+ reg |= (v) << i; \
+ mask |= 1 << i; \
+ } \
+ } \
+ VOP_INTR_SET_MASK(vop, name, mask, reg); \
+ } while (0)
+#define VOP_INTR_GET_TYPE(vop, name, type) \
+ vop_get_intr_type(vop, &vop->data->intr->name, type)
+
+#define VOP_CTRL_GET(x, name) \
+ vop_read_reg(x, 0, &vop->data->ctrl->name)
#define VOP_WIN_GET(x, win, name) \
- vop_read_reg(x, win->base, &win->phy->name)
+ vop_read_reg(x, win->offset, &VOP_WIN_NAME(win, name))
+
+#define VOP_WIN_NAME(win, name) \
+ (vop_get_win_phy(win, &win->phy->name)->name)
#define VOP_WIN_GET_YRGBADDR(vop, win) \
- vop_readl(vop, win->base + win->phy->yrgb_mst.offset)
+ vop_readl(vop, win->offset + VOP_WIN_NAME(win, yrgb_mst).offset)
#define to_vop(x) container_of(x, struct vop, crtc)
#define to_vop_win(x) container_of(x, struct vop_win, base)
+#define to_vop_plane_state(x) container_of(x, struct vop_plane_state, base)
+
+struct vop_zpos {
+ int win_id;
+ int zpos;
+};
-struct vop_win_state {
- struct list_head head;
- struct drm_framebuffer *fb;
+enum vop_pending {
+ VOP_PENDING_FB_UNREF,
+};
+
+struct vop_plane_state {
+ struct drm_plane_state base;
+ int format;
+ int zpos;
+ unsigned int logo_ymirror;
+ struct drm_rect src;
+ struct drm_rect dest;
dma_addr_t yrgb_mst;
- struct drm_pending_vblank_event *event;
+ dma_addr_t uv_mst;
+ const uint32_t *y2r_table;
+ const uint32_t *r2r_table;
+ const uint32_t *r2y_table;
+ bool enable;
};
struct vop_win {
+ struct vop_win *parent;
struct drm_plane base;
- const struct vop_win_data *data;
+
+ int win_id;
+ int area_id;
+ uint32_t offset;
+ enum drm_plane_type type;
+ const struct vop_win_phy *phy;
+ const struct vop_csc *csc;
+ const uint32_t *data_formats;
+ uint32_t nformats;
struct vop *vop;
- struct list_head pending;
- struct vop_win_state *active;
+ struct drm_property *rotation_prop;
+ struct vop_plane_state state;
};
struct vop {
struct drm_crtc crtc;
struct device *dev;
struct drm_device *drm_dev;
+ struct drm_property *plane_zpos_prop;
+ struct drm_property *plane_feature_prop;
+ struct drm_property *feature_prop;
+ bool is_iommu_enabled;
+ bool is_iommu_needed;
bool is_enabled;
- int connector_type;
- int connector_out_mode;
-
/* mutex vsync_ work */
struct mutex vsync_mutex;
bool vsync_work_pending;
+ bool loader_protect;
struct completion dsp_hold_completion;
+ /* protected by dev->event_lock */
+ struct drm_pending_vblank_event *event;
+
+ struct drm_flip_work fb_unref_work;
+ unsigned long pending;
+
+ struct completion line_flag_completion;
+
const struct vop_data *data;
+ int num_wins;
uint32_t *regsbak;
void __iomem *regs;
/* physical map length of vop register */
uint32_t len;
+ void __iomem *lut_regs;
+ u32 *lut;
+ u32 lut_len;
+ bool lut_active;
+ void __iomem *cabc_lut_regs;
+ u32 cabc_lut_len;
+
/* one time only one process allowed to config the register */
spinlock_t reg_lock;
/* lock vop irq reg */
spinlock_t irq_lock;
+ /* mutex vop enable and disable */
+ struct mutex vop_lock;
unsigned int irq;
struct clk *dclk;
/* vop share memory frequency */
struct clk *aclk;
+ /* vop source handling, optional */
+ struct clk *dclk_source;
/* vop dclk reset */
struct reset_control *dclk_rst;
- int pipe;
+ struct devfreq *devfreq;
+ struct notifier_block dmc_nb;
struct vop_win win[];
};
-enum vop_data_format {
- VOP_FMT_ARGB8888 = 0,
- VOP_FMT_RGB888,
- VOP_FMT_RGB565,
- VOP_FMT_YUV420SP = 4,
- VOP_FMT_YUV422SP,
- VOP_FMT_YUV444SP,
-};
+struct vop *dmc_vop;
-struct vop_reg_data {
- uint32_t offset;
- uint32_t value;
-};
+static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
+{
+ writel(v, vop->regs + offset);
+ vop->regsbak[offset >> 2] = v;
+}
-struct vop_reg {
- uint32_t offset;
- uint32_t shift;
- uint32_t mask;
-};
+static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
+{
+ return readl(vop->regs + offset);
+}
-struct vop_ctrl {
- struct vop_reg standby;
- struct vop_reg data_blank;
- struct vop_reg gate_en;
- struct vop_reg mmu_en;
- struct vop_reg rgb_en;
- struct vop_reg edp_en;
- struct vop_reg hdmi_en;
- struct vop_reg mipi_en;
- struct vop_reg out_mode;
- struct vop_reg dither_down;
- struct vop_reg dither_up;
- struct vop_reg pin_pol;
-
- struct vop_reg htotal_pw;
- struct vop_reg hact_st_end;
- struct vop_reg vtotal_pw;
- struct vop_reg vact_st_end;
- struct vop_reg hpost_st_end;
- struct vop_reg vpost_st_end;
-};
+static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
+ const struct vop_reg *reg)
+{
+ return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
+}
-struct vop_scl_regs {
- struct vop_reg cbcr_vsd_mode;
- struct vop_reg cbcr_vsu_mode;
- struct vop_reg cbcr_hsd_mode;
- struct vop_reg cbcr_ver_scl_mode;
- struct vop_reg cbcr_hor_scl_mode;
- struct vop_reg yrgb_vsd_mode;
- struct vop_reg yrgb_vsu_mode;
- struct vop_reg yrgb_hsd_mode;
- struct vop_reg yrgb_ver_scl_mode;
- struct vop_reg yrgb_hor_scl_mode;
- struct vop_reg line_load_mode;
- struct vop_reg cbcr_axi_gather_num;
- struct vop_reg yrgb_axi_gather_num;
- struct vop_reg vsd_cbcr_gt2;
- struct vop_reg vsd_cbcr_gt4;
- struct vop_reg vsd_yrgb_gt2;
- struct vop_reg vsd_yrgb_gt4;
- struct vop_reg bic_coe_sel;
- struct vop_reg cbcr_axi_gather_en;
- struct vop_reg yrgb_axi_gather_en;
-
- struct vop_reg lb_mode;
- struct vop_reg scale_yrgb_x;
- struct vop_reg scale_yrgb_y;
- struct vop_reg scale_cbcr_x;
- struct vop_reg scale_cbcr_y;
-};
+static inline void vop_mask_write(struct vop *vop, uint32_t offset,
+ uint32_t mask, uint32_t shift, uint32_t v,
+ bool write_mask, bool relaxed)
+{
+ if (!mask)
+ return;
-struct vop_win_phy {
- const struct vop_scl_regs *scl;
- const uint32_t *data_formats;
- uint32_t nformats;
+ if (write_mask) {
+ v = ((v & mask) << shift) | (mask << (shift + 16));
+ } else {
+ uint32_t cached_val = vop->regsbak[offset >> 2];
- struct vop_reg enable;
- struct vop_reg format;
- struct vop_reg rb_swap;
- struct vop_reg act_info;
- struct vop_reg dsp_info;
- struct vop_reg dsp_st;
- struct vop_reg yrgb_mst;
- struct vop_reg uv_mst;
- struct vop_reg yrgb_vir;
- struct vop_reg uv_vir;
-
- struct vop_reg dst_alpha_ctl;
- struct vop_reg src_alpha_ctl;
-};
+ v = (cached_val & ~(mask << shift)) | ((v & mask) << shift);
+ vop->regsbak[offset >> 2] = v;
+ }
-struct vop_win_data {
- uint32_t base;
- const struct vop_win_phy *phy;
- enum drm_plane_type type;
-};
+ if (relaxed)
+ writel_relaxed(v, vop->regs + offset);
+ else
+ writel(v, vop->regs + offset);
+}
-struct vop_data {
- const struct vop_reg_data *init_table;
- unsigned int table_size;
- const struct vop_ctrl *ctrl;
- const struct vop_win_data *win;
- unsigned int win_size;
-};
+static inline const struct vop_win_phy *
+vop_get_win_phy(struct vop_win *win, const struct vop_reg *reg)
+{
+ if (!reg->mask && win->parent)
+ return win->parent->phy;
-static const uint32_t formats_01[] = {
- DRM_FORMAT_XRGB8888,
- DRM_FORMAT_ARGB8888,
- DRM_FORMAT_XBGR8888,
- DRM_FORMAT_ABGR8888,
- DRM_FORMAT_RGB888,
- DRM_FORMAT_BGR888,
- DRM_FORMAT_RGB565,
- DRM_FORMAT_BGR565,
- DRM_FORMAT_NV12,
- DRM_FORMAT_NV16,
- DRM_FORMAT_NV24,
-};
+ return win->phy;
+}
-static const uint32_t formats_234[] = {
- DRM_FORMAT_XRGB8888,
- DRM_FORMAT_ARGB8888,
- DRM_FORMAT_XBGR8888,
- DRM_FORMAT_ABGR8888,
- DRM_FORMAT_RGB888,
- DRM_FORMAT_BGR888,
- DRM_FORMAT_RGB565,
- DRM_FORMAT_BGR565,
-};
+static inline uint32_t vop_get_intr_type(struct vop *vop,
+ const struct vop_reg *reg, int type)
+{
+ uint32_t i, ret = 0;
+ uint32_t regs = vop_read_reg(vop, 0, reg);
-static const struct vop_scl_regs win_full_scl = {
- .cbcr_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 31),
- .cbcr_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 30),
- .cbcr_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 28),
- .cbcr_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 26),
- .cbcr_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 24),
- .yrgb_vsd_mode = VOP_REG(WIN0_CTRL1, 0x1, 23),
- .yrgb_vsu_mode = VOP_REG(WIN0_CTRL1, 0x1, 22),
- .yrgb_hsd_mode = VOP_REG(WIN0_CTRL1, 0x3, 20),
- .yrgb_ver_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 18),
- .yrgb_hor_scl_mode = VOP_REG(WIN0_CTRL1, 0x3, 16),
- .line_load_mode = VOP_REG(WIN0_CTRL1, 0x1, 15),
- .cbcr_axi_gather_num = VOP_REG(WIN0_CTRL1, 0x7, 12),
- .yrgb_axi_gather_num = VOP_REG(WIN0_CTRL1, 0xf, 8),
- .vsd_cbcr_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 7),
- .vsd_cbcr_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 6),
- .vsd_yrgb_gt2 = VOP_REG(WIN0_CTRL1, 0x1, 5),
- .vsd_yrgb_gt4 = VOP_REG(WIN0_CTRL1, 0x1, 4),
- .bic_coe_sel = VOP_REG(WIN0_CTRL1, 0x3, 2),
- .cbcr_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 1),
- .yrgb_axi_gather_en = VOP_REG(WIN0_CTRL1, 0x1, 0),
- .lb_mode = VOP_REG(WIN0_CTRL0, 0x7, 5),
- .scale_yrgb_x = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
- .scale_yrgb_y = VOP_REG(WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
- .scale_cbcr_x = VOP_REG(WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
- .scale_cbcr_y = VOP_REG(WIN0_SCL_FACTOR_CBR, 0xffff, 16),
-};
+ for (i = 0; i < vop->data->intr->nintrs; i++) {
+ if ((type & vop->data->intr->intrs[i]) && (regs & 1 << i))
+ ret |= vop->data->intr->intrs[i];
+ }
-static const struct vop_win_phy win01_data = {
- .scl = &win_full_scl,
- .data_formats = formats_01,
- .nformats = ARRAY_SIZE(formats_01),
- .enable = VOP_REG(WIN0_CTRL0, 0x1, 0),
- .format = VOP_REG(WIN0_CTRL0, 0x7, 1),
- .rb_swap = VOP_REG(WIN0_CTRL0, 0x1, 12),
- .act_info = VOP_REG(WIN0_ACT_INFO, 0x1fff1fff, 0),
- .dsp_info = VOP_REG(WIN0_DSP_INFO, 0x0fff0fff, 0),
- .dsp_st = VOP_REG(WIN0_DSP_ST, 0x1fff1fff, 0),
- .yrgb_mst = VOP_REG(WIN0_YRGB_MST, 0xffffffff, 0),
- .uv_mst = VOP_REG(WIN0_CBR_MST, 0xffffffff, 0),
- .yrgb_vir = VOP_REG(WIN0_VIR, 0x3fff, 0),
- .uv_vir = VOP_REG(WIN0_VIR, 0x3fff, 16),
- .src_alpha_ctl = VOP_REG(WIN0_SRC_ALPHA_CTRL, 0xff, 0),
- .dst_alpha_ctl = VOP_REG(WIN0_DST_ALPHA_CTRL, 0xff, 0),
-};
+ return ret;
+}
-static const struct vop_win_phy win23_data = {
- .data_formats = formats_234,
- .nformats = ARRAY_SIZE(formats_234),
- .enable = VOP_REG(WIN2_CTRL0, 0x1, 0),
- .format = VOP_REG(WIN2_CTRL0, 0x7, 1),
- .rb_swap = VOP_REG(WIN2_CTRL0, 0x1, 12),
- .dsp_info = VOP_REG(WIN2_DSP_INFO0, 0x0fff0fff, 0),
- .dsp_st = VOP_REG(WIN2_DSP_ST0, 0x1fff1fff, 0),
- .yrgb_mst = VOP_REG(WIN2_MST0, 0xffffffff, 0),
- .yrgb_vir = VOP_REG(WIN2_VIR0_1, 0x1fff, 0),
- .src_alpha_ctl = VOP_REG(WIN2_SRC_ALPHA_CTRL, 0xff, 0),
- .dst_alpha_ctl = VOP_REG(WIN2_DST_ALPHA_CTRL, 0xff, 0),
-};
+static void vop_load_csc_table(struct vop *vop, u32 offset, const u32 *table)
+{
+ int i;
-static const struct vop_ctrl ctrl_data = {
- .standby = VOP_REG(SYS_CTRL, 0x1, 22),
- .gate_en = VOP_REG(SYS_CTRL, 0x1, 23),
- .mmu_en = VOP_REG(SYS_CTRL, 0x1, 20),
- .rgb_en = VOP_REG(SYS_CTRL, 0x1, 12),
- .hdmi_en = VOP_REG(SYS_CTRL, 0x1, 13),
- .edp_en = VOP_REG(SYS_CTRL, 0x1, 14),
- .mipi_en = VOP_REG(SYS_CTRL, 0x1, 15),
- .dither_down = VOP_REG(DSP_CTRL1, 0xf, 1),
- .dither_up = VOP_REG(DSP_CTRL1, 0x1, 6),
- .data_blank = VOP_REG(DSP_CTRL0, 0x1, 19),
- .out_mode = VOP_REG(DSP_CTRL0, 0xf, 0),
- .pin_pol = VOP_REG(DSP_CTRL0, 0xf, 4),
- .htotal_pw = VOP_REG(DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
- .hact_st_end = VOP_REG(DSP_HACT_ST_END, 0x1fff1fff, 0),
- .vtotal_pw = VOP_REG(DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
- .vact_st_end = VOP_REG(DSP_VACT_ST_END, 0x1fff1fff, 0),
- .hpost_st_end = VOP_REG(POST_DSP_HACT_INFO, 0x1fff1fff, 0),
- .vpost_st_end = VOP_REG(POST_DSP_VACT_INFO, 0x1fff1fff, 0),
-};
+ if (!table)
+ return;
-static const struct vop_reg_data vop_init_reg_table[] = {
- {SYS_CTRL, 0x00c00000},
- {DSP_CTRL0, 0x00000000},
- {WIN0_CTRL0, 0x00000080},
- {WIN1_CTRL0, 0x00000080},
- /* TODO: Win2/3 support multiple area function, but we haven't found
- * a suitable way to use it yet, so let's just use them as other windows
- * with only area 0 enabled.
- */
- {WIN2_CTRL0, 0x00000010},
- {WIN3_CTRL0, 0x00000010},
-};
+ for (i = 0; i < 8; i++)
+ vop_writel(vop, offset + i * 4, table[i]);
+}
-/*
- * Note: rk3288 has a dedicated 'cursor' window, however, that window requires
- * special support to get alpha blending working. For now, just use overlay
- * window 3 for the drm cursor.
- *
- */
-static const struct vop_win_data rk3288_vop_win_data[] = {
- { .base = 0x00, .phy = &win01_data, .type = DRM_PLANE_TYPE_PRIMARY },
- { .base = 0x40, .phy = &win01_data, .type = DRM_PLANE_TYPE_OVERLAY },
- { .base = 0x00, .phy = &win23_data, .type = DRM_PLANE_TYPE_OVERLAY },
- { .base = 0x50, .phy = &win23_data, .type = DRM_PLANE_TYPE_CURSOR },
-};
+static inline void vop_cfg_done(struct vop *vop)
+{
+ VOP_CTRL_SET(vop, cfg_done, 1);
+}
-static const struct vop_data rk3288_vop = {
- .init_table = vop_init_reg_table,
- .table_size = ARRAY_SIZE(vop_init_reg_table),
- .ctrl = &ctrl_data,
- .win = rk3288_vop_win_data,
- .win_size = ARRAY_SIZE(rk3288_vop_win_data),
-};
+static bool vop_is_allwin_disabled(struct vop *vop)
+{
+ int i;
-static const struct of_device_id vop_driver_dt_match[] = {
- { .compatible = "rockchip,rk3288-vop",
- .data = &rk3288_vop },
- {},
-};
-MODULE_DEVICE_TABLE(of, vop_driver_dt_match);
+ for (i = 0; i < vop->num_wins; i++) {
+ struct vop_win *win = &vop->win[i];
-static inline void vop_writel(struct vop *vop, uint32_t offset, uint32_t v)
-{
- writel(v, vop->regs + offset);
- vop->regsbak[offset >> 2] = v;
+ if (VOP_WIN_GET(vop, win, enable) != 0)
+ return false;
+ }
+
+ return true;
}
-static inline uint32_t vop_readl(struct vop *vop, uint32_t offset)
+static bool vop_is_cfg_done_complete(struct vop *vop)
{
- return readl(vop->regs + offset);
+ return VOP_CTRL_GET(vop, cfg_done) ? false : true;
}
-static inline uint32_t vop_read_reg(struct vop *vop, uint32_t base,
- const struct vop_reg *reg)
+static bool vop_fs_irq_is_active(struct vop *vop)
{
- return (vop_readl(vop, base + reg->offset) >> reg->shift) & reg->mask;
+ return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
}
-static inline void vop_cfg_done(struct vop *vop)
+static bool vop_line_flag_is_active(struct vop *vop)
{
- writel(0x01, vop->regs + REG_CFG_DONE);
+ return VOP_INTR_GET_TYPE(vop, status, LINE_FLAG_INTR);
}
-static inline void vop_mask_write(struct vop *vop, uint32_t offset,
- uint32_t mask, uint32_t v)
+static inline void vop_write_lut(struct vop *vop, uint32_t offset, uint32_t v)
{
- if (mask) {
- uint32_t cached_val = vop->regsbak[offset >> 2];
-
- cached_val = (cached_val & ~mask) | v;
- writel(cached_val, vop->regs + offset);
- vop->regsbak[offset >> 2] = cached_val;
- }
+ writel(v, vop->lut_regs + offset);
}
-static inline void vop_mask_write_relaxed(struct vop *vop, uint32_t offset,
- uint32_t mask, uint32_t v)
+static inline uint32_t vop_read_lut(struct vop *vop, uint32_t offset)
{
- if (mask) {
- uint32_t cached_val = vop->regsbak[offset >> 2];
+ return readl(vop->lut_regs + offset);
+}
- cached_val = (cached_val & ~mask) | v;
- writel_relaxed(cached_val, vop->regs + offset);
- vop->regsbak[offset >> 2] = cached_val;
- }
+static inline void vop_write_cabc_lut(struct vop *vop, uint32_t offset, uint32_t v)
+{
+ writel(v, vop->cabc_lut_regs + offset);
}
static bool has_rb_swapped(uint32_t format)
case DRM_FORMAT_BGR565:
return VOP_FMT_RGB565;
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV12_10:
return VOP_FMT_YUV420SP;
case DRM_FORMAT_NV16:
+ case DRM_FORMAT_NV16_10:
return VOP_FMT_YUV422SP;
case DRM_FORMAT_NV24:
+ case DRM_FORMAT_NV24_10:
return VOP_FMT_YUV444SP;
default:
DRM_ERROR("unsupport format[%08x]\n", format);
}
}
+static bool is_yuv_output(uint32_t bus_format)
+{
+ switch (bus_format) {
+ case MEDIA_BUS_FMT_YUV8_1X24:
+ case MEDIA_BUS_FMT_YUV10_1X30:
+ case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
+ case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
+ return true;
+ default:
+ return false;
+ }
+}
+
static bool is_yuv_support(uint32_t format)
{
switch (format) {
case DRM_FORMAT_NV12:
+ case DRM_FORMAT_NV12_10:
case DRM_FORMAT_NV16:
+ case DRM_FORMAT_NV16_10:
case DRM_FORMAT_NV24:
+ case DRM_FORMAT_NV24_10:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool is_yuv_10bit(uint32_t format)
+{
+ switch (format) {
+ case DRM_FORMAT_NV12_10:
+ case DRM_FORMAT_NV16_10:
+ case DRM_FORMAT_NV24_10:
return true;
default:
return false;
return val;
}
-static void scl_vop_cal_scl_fac(struct vop *vop, const struct vop_win_data *win,
- uint32_t src_w, uint32_t src_h, uint32_t dst_w,
- uint32_t dst_h, uint32_t pixel_format)
+static void scl_vop_cal_scl_fac(struct vop *vop, struct vop_win *win,
+ uint32_t src_w, uint32_t src_h, uint32_t dst_w,
+ uint32_t dst_h, uint32_t pixel_format)
{
uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
uint16_t cbcr_hor_scl_mode = SCALE_NONE;
uint16_t vsu_mode;
uint16_t lb_mode;
uint32_t val;
- int vskiplines;
+ int vskiplines = 0;
+
+ if (!win->phy->scl)
+ return;
- if (dst_w > 3840) {
- DRM_ERROR("Maximum destination width (3840) exceeded\n");
+ if (!win->phy->scl->ext) {
+ VOP_SCL_SET(vop, win, scale_yrgb_x,
+ scl_cal_scale2(src_w, dst_w));
+ VOP_SCL_SET(vop, win, scale_yrgb_y,
+ scl_cal_scale2(src_h, dst_h));
+ if (is_yuv) {
+ VOP_SCL_SET(vop, win, scale_cbcr_x,
+ scl_cal_scale2(cbcr_src_w, dst_w));
+ VOP_SCL_SET(vop, win, scale_cbcr_y,
+ scl_cal_scale2(cbcr_src_h, dst_h));
+ }
return;
}
lb_mode = scl_vop_cal_lb_mode(src_w, false);
}
- VOP_SCL_SET(vop, win, lb_mode, lb_mode);
+ VOP_SCL_SET_EXT(vop, win, lb_mode, lb_mode);
if (lb_mode == LB_RGB_3840X2) {
if (yrgb_ver_scl_mode != SCALE_NONE) {
DRM_ERROR("ERROR : not allow yrgb ver scale\n");
false, vsu_mode, &vskiplines);
VOP_SCL_SET(vop, win, scale_yrgb_y, val);
- VOP_SCL_SET(vop, win, vsd_yrgb_gt4, vskiplines == 4);
- VOP_SCL_SET(vop, win, vsd_yrgb_gt2, vskiplines == 2);
+ VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt4, vskiplines == 4);
+ VOP_SCL_SET_EXT(vop, win, vsd_yrgb_gt2, vskiplines == 2);
- VOP_SCL_SET(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
- VOP_SCL_SET(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
- VOP_SCL_SET(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
- VOP_SCL_SET(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
- VOP_SCL_SET(vop, win, yrgb_vsu_mode, vsu_mode);
+ VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, yrgb_hor_scl_mode);
+ VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, yrgb_ver_scl_mode);
+ VOP_SCL_SET_EXT(vop, win, yrgb_hsd_mode, SCALE_DOWN_BIL);
+ VOP_SCL_SET_EXT(vop, win, yrgb_vsd_mode, SCALE_DOWN_BIL);
+ VOP_SCL_SET_EXT(vop, win, yrgb_vsu_mode, vsu_mode);
if (is_yuv) {
+ vskiplines = 0;
+
val = scl_vop_cal_scale(cbcr_hor_scl_mode, cbcr_src_w,
dst_w, true, 0, NULL);
VOP_SCL_SET(vop, win, scale_cbcr_x, val);
dst_h, false, vsu_mode, &vskiplines);
VOP_SCL_SET(vop, win, scale_cbcr_y, val);
- VOP_SCL_SET(vop, win, vsd_cbcr_gt4, vskiplines == 4);
- VOP_SCL_SET(vop, win, vsd_cbcr_gt2, vskiplines == 2);
- VOP_SCL_SET(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
- VOP_SCL_SET(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
- VOP_SCL_SET(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
- VOP_SCL_SET(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
- VOP_SCL_SET(vop, win, cbcr_vsu_mode, vsu_mode);
+ VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt4, vskiplines == 4);
+ VOP_SCL_SET_EXT(vop, win, vsd_cbcr_gt2, vskiplines == 2);
+ VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, cbcr_hor_scl_mode);
+ VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, cbcr_ver_scl_mode);
+ VOP_SCL_SET_EXT(vop, win, cbcr_hsd_mode, SCALE_DOWN_BIL);
+ VOP_SCL_SET_EXT(vop, win, cbcr_vsd_mode, SCALE_DOWN_BIL);
+ VOP_SCL_SET_EXT(vop, win, cbcr_vsu_mode, vsu_mode);
+ }
+}
+
+/*
+ * rk3399 colorspace path:
+ * Input Win csc Output
+ * 1. YUV(2020) --> Y2R->2020To709->R2Y --> YUV_OUTPUT(601/709)
+ * RGB --> R2Y __/
+ *
+ * 2. YUV(2020) --> bypasss --> YUV_OUTPUT(2020)
+ * RGB --> 709To2020->R2Y __/
+ *
+ * 3. YUV(2020) --> Y2R->2020To709 --> RGB_OUTPUT(709)
+ * RGB --> R2Y __/
+ *
+ * 4. YUV(601/709)-> Y2R->709To2020->R2Y --> YUV_OUTPUT(2020)
+ * RGB --> 709To2020->R2Y __/
+ *
+ * 5. YUV(601/709)-> bypass --> YUV_OUTPUT(709)
+ * RGB --> R2Y __/
+ *
+ * 6. YUV(601/709)-> bypass --> YUV_OUTPUT(601)
+ * RGB --> R2Y(601) __/
+ *
+ * 7. YUV --> Y2R(709) --> RGB_OUTPUT(709)
+ * RGB --> bypass __/
+ *
+ * 8. RGB --> 709To2020->R2Y --> YUV_OUTPUT(2020)
+ *
+ * 9. RGB --> R2Y(709) --> YUV_OUTPUT(709)
+ *
+ * 10. RGB --> R2Y(601) --> YUV_OUTPUT(601)
+ *
+ * 11. RGB --> bypass --> RGB_OUTPUT(709)
+ */
+static int vop_csc_setup(const struct vop_csc_table *csc_table,
+ bool is_input_yuv, bool is_output_yuv,
+ int input_csc, int output_csc,
+ const uint32_t **y2r_table,
+ const uint32_t **r2r_table,
+ const uint32_t **r2y_table)
+{
+ *y2r_table = NULL;
+ *r2r_table = NULL;
+ *r2y_table = NULL;
+
+ if (is_output_yuv) {
+ if (output_csc == CSC_BT2020) {
+ if (is_input_yuv) {
+ if (input_csc == CSC_BT2020)
+ return 0;
+ *y2r_table = csc_table->y2r_bt709;
+ }
+ if (input_csc != CSC_BT2020)
+ *r2r_table = csc_table->r2r_bt709_to_bt2020;
+ *r2y_table = csc_table->r2y_bt2020;
+ } else {
+ if (is_input_yuv && input_csc == CSC_BT2020)
+ *y2r_table = csc_table->y2r_bt2020;
+ if (input_csc == CSC_BT2020)
+ *r2r_table = csc_table->r2r_bt2020_to_bt709;
+ if (!is_input_yuv || *y2r_table) {
+ if (output_csc == CSC_BT709)
+ *r2y_table = csc_table->r2y_bt709;
+ else
+ *r2y_table = csc_table->r2y_bt601;
+ }
+ }
+ } else {
+ if (!is_input_yuv)
+ return 0;
+
+ /*
+ * is possible use bt2020 on rgb mode?
+ */
+ if (WARN_ON(output_csc == CSC_BT2020))
+ return -EINVAL;
+
+ if (input_csc == CSC_BT2020)
+ *y2r_table = csc_table->y2r_bt2020;
+ else if (input_csc == CSC_BT709)
+ *y2r_table = csc_table->y2r_bt709;
+ else
+ *y2r_table = csc_table->y2r_bt601;
+
+ if (input_csc == CSC_BT2020)
+ /*
+ * We don't have bt601 to bt709 table, force use bt709.
+ */
+ *r2r_table = csc_table->r2r_bt2020_to_bt709;
+ }
+
+ return 0;
+}
+
+static int vop_csc_atomic_check(struct drm_crtc *crtc,
+ struct drm_crtc_state *crtc_state)
+{
+ struct vop *vop = to_vop(crtc);
+ struct drm_atomic_state *state = crtc_state->state;
+ struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
+ const struct vop_csc_table *csc_table = vop->data->csc_table;
+ struct drm_plane_state *pstate;
+ struct drm_plane *plane;
+ bool is_input_yuv, is_output_yuv;
+ int ret;
+
+ if (!csc_table)
+ return 0;
+
+ is_output_yuv = is_yuv_output(s->bus_format);
+
+ drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
+ struct vop_plane_state *vop_plane_state;
+
+ pstate = drm_atomic_get_plane_state(state, plane);
+ if (IS_ERR(pstate))
+ return PTR_ERR(pstate);
+ vop_plane_state = to_vop_plane_state(pstate);
+
+ if (!pstate->fb)
+ continue;
+ is_input_yuv = is_yuv_support(pstate->fb->pixel_format);
+
+ /*
+ * TODO: force set input and output csc mode.
+ */
+ ret = vop_csc_setup(csc_table, is_input_yuv, is_output_yuv,
+ CSC_BT709, CSC_BT709,
+ &vop_plane_state->y2r_table,
+ &vop_plane_state->r2r_table,
+ &vop_plane_state->r2y_table);
+ if (ret)
+ return ret;
}
+
+ return 0;
}
static void vop_dsp_hold_valid_irq_enable(struct vop *vop)
{
unsigned long flags;
+ spin_lock_irqsave(&vop->irq_lock, flags);
+
+ VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
+ VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
+
+ spin_unlock_irqrestore(&vop->irq_lock, flags);
+}
+
+static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&vop->irq_lock, flags);
+
+ VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 0);
+
+ spin_unlock_irqrestore(&vop->irq_lock, flags);
+}
+
+/*
+ * (1) each frame starts at the start of the Vsync pulse which is signaled by
+ * the "FRAME_SYNC" interrupt.
+ * (2) the active data region of each frame ends at dsp_vact_end
+ * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
+ * to get "LINE_FLAG" interrupt at the end of the active on screen data.
+ *
+ * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
+ * Interrupts
+ * LINE_FLAG -------------------------------+
+ * FRAME_SYNC ----+ |
+ * | |
+ * v v
+ * | Vsync | Vbp | Vactive | Vfp |
+ * ^ ^ ^ ^
+ * | | | |
+ * | | | |
+ * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END
+ * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END
+ * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END
+ * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END
+ */
+static bool vop_line_flag_irq_is_enabled(struct vop *vop)
+{
+ uint32_t line_flag_irq;
+ unsigned long flags;
+
+ spin_lock_irqsave(&vop->irq_lock, flags);
+
+ line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
+
+ spin_unlock_irqrestore(&vop->irq_lock, flags);
+
+ return !!line_flag_irq;
+}
+
+static void vop_line_flag_irq_enable(struct vop *vop, int line_num)
+{
+ unsigned long flags;
+
if (WARN_ON(!vop->is_enabled))
return;
spin_lock_irqsave(&vop->irq_lock, flags);
- vop_mask_write(vop, INTR_CTRL0, DSP_HOLD_VALID_INTR_MASK,
- DSP_HOLD_VALID_INTR_EN(1));
+ VOP_INTR_SET(vop, line_flag_num[0], line_num);
+ VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
+ VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
spin_unlock_irqrestore(&vop->irq_lock, flags);
}
-static void vop_dsp_hold_valid_irq_disable(struct vop *vop)
+static void vop_line_flag_irq_disable(struct vop *vop)
{
unsigned long flags;
spin_lock_irqsave(&vop->irq_lock, flags);
- vop_mask_write(vop, INTR_CTRL0, DSP_HOLD_VALID_INTR_MASK,
- DSP_HOLD_VALID_INTR_EN(0));
+ VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
spin_unlock_irqrestore(&vop->irq_lock, flags);
}
-static void vop_enable(struct drm_crtc *crtc)
+static void vop_crtc_load_lut(struct drm_crtc *crtc)
{
struct vop *vop = to_vop(crtc);
- int ret;
-
- if (vop->is_enabled)
- return;
+ int i, dle, lut_idx;
- ret = pm_runtime_get_sync(vop->dev);
- if (ret < 0) {
- dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
+ if (!vop->is_enabled || !vop->lut || !vop->lut_regs)
return;
- }
- ret = clk_enable(vop->hclk);
- if (ret < 0) {
- dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
+ if (WARN_ON(!drm_modeset_is_locked(&crtc->mutex)))
return;
- }
-
- ret = clk_enable(vop->dclk);
- if (ret < 0) {
- dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
- goto err_disable_hclk;
- }
- ret = clk_enable(vop->aclk);
- if (ret < 0) {
- dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
- goto err_disable_dclk;
- }
+ if (!VOP_CTRL_SUPPORT(vop, update_gamma_lut)) {
+ spin_lock(&vop->reg_lock);
+ VOP_CTRL_SET(vop, dsp_lut_en, 0);
+ vop_cfg_done(vop);
+ spin_unlock(&vop->reg_lock);
- /*
- * Slave iommu shares power, irq and clock with vop. It was associated
- * automatically with this master device via common driver code.
- * Now that we have enabled the clock we attach it to the shared drm
- * mapping.
- */
- ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
- if (ret) {
- dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
- goto err_disable_aclk;
+#define CTRL_GET(name) VOP_CTRL_GET(vop, name)
+ readx_poll_timeout(CTRL_GET, dsp_lut_en,
+ dle, !dle, 5, 33333);
+ } else {
+ lut_idx = CTRL_GET(lut_buffer_index);
}
- memcpy(vop->regs, vop->regsbak, vop->len);
- /*
- * At here, vop clock & iommu is enable, R/W vop regs would be safe.
- */
- vop->is_enabled = true;
+ for (i = 0; i < vop->lut_len; i++)
+ vop_write_lut(vop, i << 2, vop->lut[i]);
spin_lock(&vop->reg_lock);
- VOP_CTRL_SET(vop, standby, 0);
+ VOP_CTRL_SET(vop, dsp_lut_en, 1);
+ VOP_CTRL_SET(vop, update_gamma_lut, 1);
+ vop_cfg_done(vop);
+ vop->lut_active = true;
spin_unlock(&vop->reg_lock);
- enable_irq(vop->irq);
+ if (VOP_CTRL_SUPPORT(vop, update_gamma_lut)) {
+ readx_poll_timeout(CTRL_GET, lut_buffer_index,
+ dle, dle != lut_idx, 5, 33333);
+ /* FIXME:
+ * update_gamma value auto clean to 0 by HW, should not
+ * bakeup it.
+ */
+ VOP_CTRL_SET(vop, update_gamma_lut, 0);
+ }
+#undef CTRL_GET
+}
- drm_vblank_on(vop->drm_dev, vop->pipe);
+void rockchip_vop_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
+ u16 blue, int regno)
+{
+ struct vop *vop = to_vop(crtc);
+ u32 lut_len = vop->lut_len;
+ u32 r, g, b;
- return;
+ if (regno >= lut_len || !vop->lut)
+ return;
-err_disable_aclk:
- clk_disable(vop->aclk);
-err_disable_dclk:
- clk_disable(vop->dclk);
-err_disable_hclk:
- clk_disable(vop->hclk);
+ r = red * (lut_len - 1) / 0xffff;
+ g = green * (lut_len - 1) / 0xffff;
+ b = blue * (lut_len - 1) / 0xffff;
+ vop->lut[regno] = r * lut_len * lut_len + g * lut_len + b;
}
-static void vop_disable(struct drm_crtc *crtc)
+void rockchip_vop_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
+ u16 *blue, int regno)
{
struct vop *vop = to_vop(crtc);
+ u32 lut_len = vop->lut_len;
+ u32 r, g, b;
- if (!vop->is_enabled)
+ if (regno >= lut_len || !vop->lut)
return;
- drm_vblank_off(crtc->dev, vop->pipe);
+ r = (vop->lut[regno] / lut_len / lut_len) & (lut_len - 1);
+ g = (vop->lut[regno] / lut_len) & (lut_len - 1);
+ b = vop->lut[regno] & (lut_len - 1);
+ *red = r * 0xffff / (lut_len - 1);
+ *green = g * 0xffff / (lut_len - 1);
+ *blue = b * 0xffff / (lut_len - 1);
+}
- /*
- * Vop standby will take effect at end of current frame,
- * if dsp hold valid irq happen, it means standby complete.
- *
- * we must wait standby complete when we want to disable aclk,
- * if not, memory bus maybe dead.
- */
- reinit_completion(&vop->dsp_hold_completion);
+static void vop_power_enable(struct drm_crtc *crtc)
+{
+ struct vop *vop = to_vop(crtc);
+ int ret;
+
+ ret = clk_prepare_enable(vop->hclk);
+ if (ret < 0) {
+ dev_err(vop->dev, "failed to enable hclk - %d\n", ret);
+ return;
+ }
+
+ ret = clk_prepare_enable(vop->dclk);
+ if (ret < 0) {
+ dev_err(vop->dev, "failed to enable dclk - %d\n", ret);
+ goto err_disable_hclk;
+ }
+
+ ret = clk_prepare_enable(vop->aclk);
+ if (ret < 0) {
+ dev_err(vop->dev, "failed to enable aclk - %d\n", ret);
+ goto err_disable_dclk;
+ }
+
+ ret = pm_runtime_get_sync(vop->dev);
+ if (ret < 0) {
+ dev_err(vop->dev, "failed to get pm runtime: %d\n", ret);
+ return;
+ }
+
+ memcpy(vop->regsbak, vop->regs, vop->len);
+
+ vop->is_enabled = true;
+
+ return;
+
+err_disable_dclk:
+ clk_disable_unprepare(vop->dclk);
+err_disable_hclk:
+ clk_disable_unprepare(vop->hclk);
+}
+
+static void vop_initial(struct drm_crtc *crtc)
+{
+ struct vop *vop = to_vop(crtc);
+ uint32_t irqs;
+ int i;
+
+ vop_power_enable(crtc);
+
+ VOP_CTRL_SET(vop, global_regdone_en, 1);
+ VOP_CTRL_SET(vop, dsp_blank, 0);
+
+ /*
+ * restore the lut table.
+ */
+ if (vop->lut_active)
+ vop_crtc_load_lut(crtc);
+
+ /*
+ * We need to make sure that all windows are disabled before resume
+ * the crtc. Otherwise we might try to scan from a destroyed
+ * buffer later.
+ */
+ for (i = 0; i < vop->num_wins; i++) {
+ struct vop_win *win = &vop->win[i];
+ int channel = i * 2 + 1;
+
+ VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
+ if (win->phy->scl && win->phy->scl->ext) {
+ VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
+ VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
+ VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
+ VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
+ }
+ VOP_WIN_SET(vop, win, enable, 0);
+ VOP_WIN_SET(vop, win, gate, 1);
+ }
+ VOP_CTRL_SET(vop, afbdc_en, 0);
+
+ irqs = BUS_ERROR_INTR | WIN0_EMPTY_INTR | WIN1_EMPTY_INTR |
+ WIN2_EMPTY_INTR | WIN3_EMPTY_INTR | HWC_EMPTY_INTR |
+ POST_BUF_EMPTY_INTR;
+ VOP_INTR_SET_TYPE(vop, clear, irqs, 1);
+ VOP_INTR_SET_TYPE(vop, enable, irqs, 1);
+}
+
+static void vop_crtc_disable(struct drm_crtc *crtc)
+{
+ struct vop *vop = to_vop(crtc);
+
+ mutex_lock(&vop->vop_lock);
+ drm_crtc_vblank_off(crtc);
+
+ /*
+ * Vop standby will take effect at end of current frame,
+ * if dsp hold valid irq happen, it means standby complete.
+ *
+ * we must wait standby complete when we want to disable aclk,
+ * if not, memory bus maybe dead.
+ */
+ reinit_completion(&vop->dsp_hold_completion);
vop_dsp_hold_valid_irq_enable(vop);
spin_lock(&vop->reg_lock);
spin_unlock(&vop->reg_lock);
- wait_for_completion(&vop->dsp_hold_completion);
+ WARN_ON(!wait_for_completion_timeout(&vop->dsp_hold_completion,
+ msecs_to_jiffies(50)));
vop_dsp_hold_valid_irq_disable(vop);
disable_irq(vop->irq);
vop->is_enabled = false;
+ if (vop->is_iommu_enabled) {
+ /*
+ * vop standby complete, so iommu detach is safe.
+ */
+ rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
+ vop->is_iommu_enabled = false;
+ }
- /*
- * vop standby complete, so iommu detach is safe.
- */
- rockchip_drm_dma_detach_device(vop->drm_dev, vop->dev);
-
- clk_disable(vop->dclk);
- clk_disable(vop->aclk);
- clk_disable(vop->hclk);
pm_runtime_put(vop->dev);
+ clk_disable_unprepare(vop->dclk);
+ clk_disable_unprepare(vop->aclk);
+ clk_disable_unprepare(vop->hclk);
+ mutex_unlock(&vop->vop_lock);
}
-/*
- * Caller must hold vsync_mutex.
- */
-static struct drm_framebuffer *vop_win_last_pending_fb(struct vop_win *vop_win)
+static void vop_plane_destroy(struct drm_plane *plane)
{
- struct vop_win_state *last;
- struct vop_win_state *active = vop_win->active;
-
- if (list_empty(&vop_win->pending))
- return active ? active->fb : NULL;
-
- last = list_last_entry(&vop_win->pending, struct vop_win_state, head);
- return last ? last->fb : NULL;
+ drm_plane_cleanup(plane);
}
-/*
- * Caller must hold vsync_mutex.
- */
-static int vop_win_queue_fb(struct vop_win *vop_win,
- struct drm_framebuffer *fb, dma_addr_t yrgb_mst,
- struct drm_pending_vblank_event *event)
+static int vop_plane_prepare_fb(struct drm_plane *plane,
+ const struct drm_plane_state *new_state)
{
- struct vop_win_state *state;
-
- state = kzalloc(sizeof(*state), GFP_KERNEL);
- if (!state)
- return -ENOMEM;
-
- state->fb = fb;
- state->yrgb_mst = yrgb_mst;
- state->event = event;
-
- list_add_tail(&state->head, &vop_win->pending);
+ if (plane->state->fb)
+ drm_framebuffer_reference(plane->state->fb);
return 0;
}
-static int vop_update_plane_event(struct drm_plane *plane,
- struct drm_crtc *crtc,
- struct drm_framebuffer *fb, int crtc_x,
- int crtc_y, unsigned int crtc_w,
- unsigned int crtc_h, uint32_t src_x,
- uint32_t src_y, uint32_t src_w,
- uint32_t src_h,
- struct drm_pending_vblank_event *event)
+static void vop_plane_cleanup_fb(struct drm_plane *plane,
+ const struct drm_plane_state *old_state)
{
- struct vop_win *vop_win = to_vop_win(plane);
- const struct vop_win_data *win = vop_win->data;
- struct vop *vop = to_vop(crtc);
- struct drm_gem_object *obj;
- struct rockchip_gem_object *rk_obj;
- struct drm_gem_object *uv_obj;
- struct rockchip_gem_object *rk_uv_obj;
- unsigned long offset;
- unsigned int actual_w;
- unsigned int actual_h;
- unsigned int dsp_stx;
- unsigned int dsp_sty;
- unsigned int y_vir_stride;
- unsigned int uv_vir_stride = 0;
- dma_addr_t yrgb_mst;
- dma_addr_t uv_mst = 0;
- enum vop_data_format format;
- uint32_t val;
- bool is_alpha;
- bool rb_swap;
- bool is_yuv;
+ if (old_state->fb)
+ drm_framebuffer_unreference(old_state->fb);
+}
+
+static int vop_plane_atomic_check(struct drm_plane *plane,
+ struct drm_plane_state *state)
+{
+ struct drm_crtc *crtc = state->crtc;
+ struct drm_framebuffer *fb = state->fb;
+ struct vop_win *win = to_vop_win(plane);
+ struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
+ struct drm_crtc_state *crtc_state;
+ const struct vop_data *vop_data;
+ struct vop *vop;
bool visible;
int ret;
- struct drm_rect dest = {
- .x1 = crtc_x,
- .y1 = crtc_y,
- .x2 = crtc_x + crtc_w,
- .y2 = crtc_y + crtc_h,
- };
- struct drm_rect src = {
- /* 16.16 fixed point */
- .x1 = src_x,
- .y1 = src_y,
- .x2 = src_x + src_w,
- .y2 = src_y + src_h,
- };
- const struct drm_rect clip = {
- .x2 = crtc->mode.hdisplay,
- .y2 = crtc->mode.vdisplay,
- };
- bool can_position = plane->type != DRM_PLANE_TYPE_PRIMARY;
+ struct drm_rect *dest = &vop_plane_state->dest;
+ struct drm_rect *src = &vop_plane_state->src;
+ struct drm_rect clip;
int min_scale = win->phy->scl ? FRAC_16_16(1, 8) :
DRM_PLANE_HELPER_NO_SCALING;
int max_scale = win->phy->scl ? FRAC_16_16(8, 1) :
DRM_PLANE_HELPER_NO_SCALING;
+ unsigned long offset;
+ dma_addr_t dma_addr;
+ u16 vdisplay;
- ret = drm_plane_helper_check_update(plane, crtc, fb,
- &src, &dest, &clip,
+ crtc = crtc ? crtc : plane->state->crtc;
+ /*
+ * Both crtc or plane->state->crtc can be null.
+ */
+ if (!crtc || !fb)
+ goto out_disable;
+
+ crtc_state = drm_atomic_get_crtc_state(state->state, crtc);
+ if (IS_ERR(crtc_state))
+ return PTR_ERR(crtc_state);
+
+ src->x1 = state->src_x;
+ src->y1 = state->src_y;
+ src->x2 = state->src_x + state->src_w;
+ src->y2 = state->src_y + state->src_h;
+ dest->x1 = state->crtc_x;
+ dest->y1 = state->crtc_y;
+ dest->x2 = state->crtc_x + state->crtc_w;
+ dest->y2 = state->crtc_y + state->crtc_h;
+
+ vdisplay = crtc_state->adjusted_mode.crtc_vdisplay;
+ if (crtc_state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
+ vdisplay *= 2;
+
+ clip.x1 = 0;
+ clip.y1 = 0;
+ clip.x2 = crtc_state->adjusted_mode.crtc_hdisplay;
+ clip.y2 = vdisplay;
+
+ ret = drm_plane_helper_check_update(plane, crtc, state->fb,
+ src, dest, &clip,
min_scale,
max_scale,
- can_position, false, &visible);
+ true, true, &visible);
if (ret)
return ret;
if (!visible)
- return 0;
-
- is_alpha = is_alpha_support(fb->pixel_format);
- rb_swap = has_rb_swapped(fb->pixel_format);
- is_yuv = is_yuv_support(fb->pixel_format);
-
- format = vop_convert_format(fb->pixel_format);
- if (format < 0)
- return format;
+ goto out_disable;
+
+ vop_plane_state->format = vop_convert_format(fb->pixel_format);
+ if (vop_plane_state->format < 0)
+ return vop_plane_state->format;
+
+ vop = to_vop(crtc);
+ vop_data = vop->data;
+
+ if (drm_rect_width(src) >> 16 > vop_data->max_input.width ||
+ drm_rect_height(src) >> 16 > vop_data->max_input.height) {
+ DRM_ERROR("Invalid source: %dx%d. max input: %dx%d\n",
+ drm_rect_width(src) >> 16,
+ drm_rect_height(src) >> 16,
+ vop_data->max_input.width,
+ vop_data->max_input.height);
+ return -EINVAL;
+ }
- obj = rockchip_fb_get_gem_obj(fb, 0);
- if (!obj) {
- DRM_ERROR("fail to get rockchip gem object from framebuffer\n");
+ /*
+ * Src.x1 can be odd when do clip, but yuv plane start point
+ * need align with 2 pixel.
+ */
+ if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2)) {
+ DRM_ERROR("Invalid Source: Yuv format Can't support odd xpos\n");
return -EINVAL;
}
- rk_obj = to_rockchip_obj(obj);
+ offset = (src->x1 >> 16) * drm_format_plane_bpp(fb->pixel_format, 0) / 8;
+ if (state->rotation & BIT(DRM_REFLECT_Y) ||
+ (rockchip_fb_is_logo(fb) && vop_plane_state->logo_ymirror))
+ offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
+ else
+ offset += (src->y1 >> 16) * fb->pitches[0];
- if (is_yuv) {
- /*
- * Src.x1 can be odd when do clip, but yuv plane start point
- * need align with 2 pixel.
- */
- val = (src.x1 >> 16) % 2;
- src.x1 += val << 16;
- src.x2 += val << 16;
- }
+ dma_addr = rockchip_fb_get_dma_addr(fb, 0);
+ vop_plane_state->yrgb_mst = dma_addr + offset + fb->offsets[0];
+ if (is_yuv_support(fb->pixel_format)) {
+ int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
+ int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
+ int bpp = drm_format_plane_bpp(fb->pixel_format, 1);
- actual_w = (src.x2 - src.x1) >> 16;
- actual_h = (src.y2 - src.y1) >> 16;
+ offset = (src->x1 >> 16) * bpp / hsub / 8;
+ offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
- dsp_stx = dest.x1 + crtc->mode.htotal - crtc->mode.hsync_start;
- dsp_sty = dest.y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
+ dma_addr = rockchip_fb_get_dma_addr(fb, 1);
+ dma_addr += offset + fb->offsets[1];
+ vop_plane_state->uv_mst = dma_addr;
+ }
- offset = (src.x1 >> 16) * drm_format_plane_cpp(fb->pixel_format, 0);
- offset += (src.y1 >> 16) * fb->pitches[0];
+ vop_plane_state->enable = true;
- yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0];
- y_vir_stride = fb->pitches[0] >> 2;
+ return 0;
- if (is_yuv) {
- int hsub = drm_format_horz_chroma_subsampling(fb->pixel_format);
- int vsub = drm_format_vert_chroma_subsampling(fb->pixel_format);
- int bpp = drm_format_plane_cpp(fb->pixel_format, 1);
+out_disable:
+ vop_plane_state->enable = false;
+ return 0;
+}
- uv_obj = rockchip_fb_get_gem_obj(fb, 1);
- if (!uv_obj) {
- DRM_ERROR("fail to get uv object from framebuffer\n");
- return -EINVAL;
- }
- rk_uv_obj = to_rockchip_obj(uv_obj);
- uv_vir_stride = fb->pitches[1] >> 2;
+static void vop_plane_atomic_disable(struct drm_plane *plane,
+ struct drm_plane_state *old_state)
+{
+ struct vop_plane_state *vop_plane_state = to_vop_plane_state(old_state);
+ struct vop_win *win = to_vop_win(plane);
+ struct vop *vop = to_vop(old_state->crtc);
- offset = (src.x1 >> 16) * bpp / hsub;
- offset += (src.y1 >> 16) * fb->pitches[1] / vsub;
+ if (!old_state->crtc)
+ return;
- uv_mst = rk_uv_obj->dma_addr + offset + fb->offsets[1];
- }
+ spin_lock(&vop->reg_lock);
/*
- * If this plane update changes the plane's framebuffer, (or more
- * precisely, if this update has a different framebuffer than the last
- * update), enqueue it so we can track when it completes.
- *
- * Only when we discover that this update has completed, can we
- * unreference any previous framebuffers.
+ * FIXUP: some of the vop scale would be abnormal after windows power
+ * on/off so deinit scale to scale_none mode.
*/
- mutex_lock(&vop->vsync_mutex);
- if (fb != vop_win_last_pending_fb(vop_win)) {
- ret = drm_vblank_get(plane->dev, vop->pipe);
- if (ret) {
- DRM_ERROR("failed to get vblank, %d\n", ret);
- mutex_unlock(&vop->vsync_mutex);
- return ret;
- }
+ if (win->phy->scl && win->phy->scl->ext) {
+ VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
+ VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
+ VOP_SCL_SET_EXT(vop, win, cbcr_hor_scl_mode, SCALE_NONE);
+ VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
+ }
+ VOP_WIN_SET(vop, win, enable, 0);
- drm_framebuffer_reference(fb);
+ spin_unlock(&vop->reg_lock);
- ret = vop_win_queue_fb(vop_win, fb, yrgb_mst, event);
- if (ret) {
- drm_vblank_put(plane->dev, vop->pipe);
- mutex_unlock(&vop->vsync_mutex);
- return ret;
- }
+ vop_plane_state->enable = false;
+}
+
+static void vop_plane_atomic_update(struct drm_plane *plane,
+ struct drm_plane_state *old_state)
+{
+ struct drm_plane_state *state = plane->state;
+ struct drm_crtc *crtc = state->crtc;
+ struct vop_win *win = to_vop_win(plane);
+ struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
+ struct rockchip_crtc_state *s;
+ struct vop *vop;
+ struct drm_framebuffer *fb = state->fb;
+ unsigned int actual_w, actual_h;
+ unsigned int dsp_stx, dsp_sty;
+ uint32_t act_info, dsp_info, dsp_st;
+ struct drm_rect *src = &vop_plane_state->src;
+ struct drm_rect *dest = &vop_plane_state->dest;
+ const uint32_t *y2r_table = vop_plane_state->y2r_table;
+ const uint32_t *r2r_table = vop_plane_state->r2r_table;
+ const uint32_t *r2y_table = vop_plane_state->r2y_table;
+ int ymirror, xmirror;
+ uint32_t val;
+ bool rb_swap;
+
+ /*
+ * can't update plane when vop is disabled.
+ */
+ if (!crtc)
+ return;
- vop->vsync_work_pending = true;
+ if (!vop_plane_state->enable) {
+ vop_plane_atomic_disable(plane, old_state);
+ return;
}
- mutex_unlock(&vop->vsync_mutex);
+
+ actual_w = drm_rect_width(src) >> 16;
+ actual_h = drm_rect_height(src) >> 16;
+ act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
+
+ dsp_info = (drm_rect_height(dest) - 1) << 16;
+ dsp_info |= (drm_rect_width(dest) - 1) & 0xffff;
+
+ dsp_stx = dest->x1 + crtc->mode.htotal - crtc->mode.hsync_start;
+ dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
+ dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
+
+ ymirror = state->rotation & BIT(DRM_REFLECT_Y) ||
+ (rockchip_fb_is_logo(fb) && vop_plane_state->logo_ymirror);
+ xmirror = !!(state->rotation & BIT(DRM_REFLECT_X));
+
+ vop = to_vop(state->crtc);
+ s = to_rockchip_crtc_state(crtc->state);
spin_lock(&vop->reg_lock);
- VOP_WIN_SET(vop, win, format, format);
- VOP_WIN_SET(vop, win, yrgb_vir, y_vir_stride);
- VOP_WIN_SET(vop, win, yrgb_mst, yrgb_mst);
- if (is_yuv) {
- VOP_WIN_SET(vop, win, uv_vir, uv_vir_stride);
- VOP_WIN_SET(vop, win, uv_mst, uv_mst);
+ VOP_WIN_SET(vop, win, xmirror, xmirror);
+ VOP_WIN_SET(vop, win, ymirror, ymirror);
+ VOP_WIN_SET(vop, win, format, vop_plane_state->format);
+ VOP_WIN_SET(vop, win, yrgb_vir, fb->pitches[0] >> 2);
+ VOP_WIN_SET(vop, win, yrgb_mst, vop_plane_state->yrgb_mst);
+ if (is_yuv_support(fb->pixel_format)) {
+ VOP_WIN_SET(vop, win, uv_vir, fb->pitches[1] >> 2);
+ VOP_WIN_SET(vop, win, uv_mst, vop_plane_state->uv_mst);
}
+ VOP_WIN_SET(vop, win, fmt_10, is_yuv_10bit(fb->pixel_format));
- if (win->phy->scl)
- scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
- dest.x2 - dest.x1, dest.y2 - dest.y1,
- fb->pixel_format);
-
- val = (actual_h - 1) << 16;
- val |= (actual_w - 1) & 0xffff;
- VOP_WIN_SET(vop, win, act_info, val);
-
- val = (dest.y2 - dest.y1 - 1) << 16;
- val |= (dest.x2 - dest.x1 - 1) & 0xffff;
- VOP_WIN_SET(vop, win, dsp_info, val);
- val = dsp_sty << 16;
- val |= dsp_stx & 0xffff;
- VOP_WIN_SET(vop, win, dsp_st, val);
+ scl_vop_cal_scl_fac(vop, win, actual_w, actual_h,
+ drm_rect_width(dest), drm_rect_height(dest),
+ fb->pixel_format);
+
+ VOP_WIN_SET(vop, win, act_info, act_info);
+ VOP_WIN_SET(vop, win, dsp_info, dsp_info);
+ VOP_WIN_SET(vop, win, dsp_st, dsp_st);
+
+ rb_swap = has_rb_swapped(fb->pixel_format);
VOP_WIN_SET(vop, win, rb_swap, rb_swap);
- if (is_alpha) {
+ if (is_alpha_support(fb->pixel_format) &&
+ (s->dsp_layer_sel & 0x3) != win->win_id) {
VOP_WIN_SET(vop, win, dst_alpha_ctl,
DST_FACTOR_M0(ALPHA_SRC_INVERSE));
val = SRC_ALPHA_EN(1) | SRC_COLOR_M0(ALPHA_SRC_PRE_MUL) |
SRC_ALPHA_CAL_M0(ALPHA_NO_SATURATION) |
SRC_FACTOR_M0(ALPHA_ONE);
VOP_WIN_SET(vop, win, src_alpha_ctl, val);
+ VOP_WIN_SET(vop, win, alpha_mode, 1);
+ VOP_WIN_SET(vop, win, alpha_en, 1);
} else {
VOP_WIN_SET(vop, win, src_alpha_ctl, SRC_ALPHA_EN(0));
+ VOP_WIN_SET(vop, win, alpha_en, 0);
}
+ if (win->csc) {
+ vop_load_csc_table(vop, win->csc->y2r_offset, y2r_table);
+ vop_load_csc_table(vop, win->csc->r2r_offset, r2r_table);
+ vop_load_csc_table(vop, win->csc->r2y_offset, r2y_table);
+ VOP_WIN_SET_EXT(vop, win, csc, y2r_en, !!y2r_table);
+ VOP_WIN_SET_EXT(vop, win, csc, r2r_en, !!r2r_table);
+ VOP_WIN_SET_EXT(vop, win, csc, r2y_en, !!r2y_table);
+ }
VOP_WIN_SET(vop, win, enable, 1);
-
- vop_cfg_done(vop);
spin_unlock(&vop->reg_lock);
-
- return 0;
+ vop->is_iommu_needed = true;
}
-static int vop_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
- struct drm_framebuffer *fb, int crtc_x, int crtc_y,
- unsigned int crtc_w, unsigned int crtc_h,
- uint32_t src_x, uint32_t src_y, uint32_t src_w,
- uint32_t src_h)
+static const struct drm_plane_helper_funcs plane_helper_funcs = {
+ .prepare_fb = vop_plane_prepare_fb,
+ .cleanup_fb = vop_plane_cleanup_fb,
+ .atomic_check = vop_plane_atomic_check,
+ .atomic_update = vop_plane_atomic_update,
+ .atomic_disable = vop_plane_atomic_disable,
+};
+
+void vop_atomic_plane_reset(struct drm_plane *plane)
{
- return vop_update_plane_event(plane, crtc, fb, crtc_x, crtc_y, crtc_w,
- crtc_h, src_x, src_y, src_w, src_h,
- NULL);
+ struct vop_win *win = to_vop_win(plane);
+ struct vop_plane_state *vop_plane_state =
+ to_vop_plane_state(plane->state);
+
+ if (plane->state && plane->state->fb)
+ drm_framebuffer_unreference(plane->state->fb);
+
+ kfree(vop_plane_state);
+ vop_plane_state = kzalloc(sizeof(*vop_plane_state), GFP_KERNEL);
+ if (!vop_plane_state)
+ return;
+
+ vop_plane_state->zpos = win->win_id;
+ plane->state = &vop_plane_state->base;
+ plane->state->plane = plane;
}
-static int vop_update_primary_plane(struct drm_crtc *crtc,
- struct drm_pending_vblank_event *event)
+struct drm_plane_state *
+vop_atomic_plane_duplicate_state(struct drm_plane *plane)
{
- unsigned int crtc_w, crtc_h;
+ struct vop_plane_state *old_vop_plane_state;
+ struct vop_plane_state *vop_plane_state;
- crtc_w = crtc->primary->fb->width - crtc->x;
- crtc_h = crtc->primary->fb->height - crtc->y;
+ if (WARN_ON(!plane->state))
+ return NULL;
- return vop_update_plane_event(crtc->primary, crtc, crtc->primary->fb,
- 0, 0, crtc_w, crtc_h, crtc->x << 16,
- crtc->y << 16, crtc_w << 16,
- crtc_h << 16, event);
+ old_vop_plane_state = to_vop_plane_state(plane->state);
+ vop_plane_state = kmemdup(old_vop_plane_state,
+ sizeof(*vop_plane_state), GFP_KERNEL);
+ if (!vop_plane_state)
+ return NULL;
+
+ __drm_atomic_helper_plane_duplicate_state(plane,
+ &vop_plane_state->base);
+
+ return &vop_plane_state->base;
}
-static int vop_disable_plane(struct drm_plane *plane)
+static void vop_atomic_plane_destroy_state(struct drm_plane *plane,
+ struct drm_plane_state *state)
{
- struct vop_win *vop_win = to_vop_win(plane);
- const struct vop_win_data *win = vop_win->data;
- struct vop *vop;
- int ret;
+ struct vop_plane_state *vop_state = to_vop_plane_state(state);
- if (!plane->crtc)
- return 0;
-
- vop = to_vop(plane->crtc);
+ __drm_atomic_helper_plane_destroy_state(plane, state);
- ret = drm_vblank_get(plane->dev, vop->pipe);
- if (ret) {
- DRM_ERROR("failed to get vblank, %d\n", ret);
- return ret;
- }
+ kfree(vop_state);
+}
- mutex_lock(&vop->vsync_mutex);
+static int vop_atomic_plane_set_property(struct drm_plane *plane,
+ struct drm_plane_state *state,
+ struct drm_property *property,
+ uint64_t val)
+{
+ struct rockchip_drm_private *private = plane->dev->dev_private;
+ struct vop_win *win = to_vop_win(plane);
+ struct vop_plane_state *plane_state = to_vop_plane_state(state);
- ret = vop_win_queue_fb(vop_win, NULL, 0, NULL);
- if (ret) {
- drm_vblank_put(plane->dev, vop->pipe);
- mutex_unlock(&vop->vsync_mutex);
- return ret;
+ if (property == win->vop->plane_zpos_prop) {
+ plane_state->zpos = val;
+ return 0;
}
- vop->vsync_work_pending = true;
- mutex_unlock(&vop->vsync_mutex);
+ if (property == win->rotation_prop) {
+ state->rotation = val;
+ return 0;
+ }
- spin_lock(&vop->reg_lock);
- VOP_WIN_SET(vop, win, enable, 0);
- vop_cfg_done(vop);
- spin_unlock(&vop->reg_lock);
+ if (property == private->logo_ymirror_prop) {
+ WARN_ON(!rockchip_fb_is_logo(state->fb));
+ plane_state->logo_ymirror = val;
+ return 0;
+ }
- return 0;
+ DRM_ERROR("failed to set vop plane property\n");
+ return -EINVAL;
}
-static void vop_plane_destroy(struct drm_plane *plane)
+static int vop_atomic_plane_get_property(struct drm_plane *plane,
+ const struct drm_plane_state *state,
+ struct drm_property *property,
+ uint64_t *val)
{
- vop_disable_plane(plane);
- drm_plane_cleanup(plane);
+ struct vop_win *win = to_vop_win(plane);
+ struct vop_plane_state *plane_state = to_vop_plane_state(state);
+
+ if (property == win->vop->plane_zpos_prop) {
+ *val = plane_state->zpos;
+ return 0;
+ }
+
+ if (property == win->rotation_prop) {
+ *val = state->rotation;
+ return 0;
+ }
+
+ DRM_ERROR("failed to get vop plane property\n");
+ return -EINVAL;
}
static const struct drm_plane_funcs vop_plane_funcs = {
- .update_plane = vop_update_plane,
- .disable_plane = vop_disable_plane,
+ .update_plane = drm_atomic_helper_update_plane,
+ .disable_plane = drm_atomic_helper_disable_plane,
.destroy = vop_plane_destroy,
+ .reset = vop_atomic_plane_reset,
+ .set_property = drm_atomic_helper_plane_set_property,
+ .atomic_duplicate_state = vop_atomic_plane_duplicate_state,
+ .atomic_destroy_state = vop_atomic_plane_destroy_state,
+ .atomic_set_property = vop_atomic_plane_set_property,
+ .atomic_get_property = vop_atomic_plane_get_property,
};
-int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc,
- int connector_type,
- int out_mode)
-{
- struct vop *vop = to_vop(crtc);
-
- vop->connector_type = connector_type;
- vop->connector_out_mode = out_mode;
-
- return 0;
-}
-EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config);
-
static int vop_crtc_enable_vblank(struct drm_crtc *crtc)
{
struct vop *vop = to_vop(crtc);
spin_lock_irqsave(&vop->irq_lock, flags);
- vop_mask_write(vop, INTR_CTRL0, FS_INTR_MASK, FS_INTR_EN(1));
+ VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
+ VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
spin_unlock_irqrestore(&vop->irq_lock, flags);
return;
spin_lock_irqsave(&vop->irq_lock, flags);
- vop_mask_write(vop, INTR_CTRL0, FS_INTR_MASK, FS_INTR_EN(0));
+
+ VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 0);
+
spin_unlock_irqrestore(&vop->irq_lock, flags);
}
-static const struct rockchip_crtc_funcs private_crtc_funcs = {
- .enable_vblank = vop_crtc_enable_vblank,
- .disable_vblank = vop_crtc_disable_vblank,
-};
-
-static void vop_crtc_dpms(struct drm_crtc *crtc, int mode)
+static void vop_crtc_cancel_pending_vblank(struct drm_crtc *crtc,
+ struct drm_file *file_priv)
{
- DRM_DEBUG_KMS("crtc[%d] mode[%d]\n", crtc->base.id, mode);
+ struct drm_device *drm = crtc->dev;
+ struct vop *vop = to_vop(crtc);
+ struct drm_pending_vblank_event *e;
+ unsigned long flags;
- switch (mode) {
- case DRM_MODE_DPMS_ON:
- vop_enable(crtc);
- break;
- case DRM_MODE_DPMS_STANDBY:
- case DRM_MODE_DPMS_SUSPEND:
- case DRM_MODE_DPMS_OFF:
- vop_disable(crtc);
- break;
- default:
- DRM_DEBUG_KMS("unspecified mode %d\n", mode);
- break;
+ spin_lock_irqsave(&drm->event_lock, flags);
+ e = vop->event;
+ if (e && e->base.file_priv == file_priv) {
+ vop->event = NULL;
+
+ e->base.destroy(&e->base);
+ file_priv->event_space += sizeof(e->event);
}
+ spin_unlock_irqrestore(&drm->event_lock, flags);
}
-static void vop_crtc_prepare(struct drm_crtc *crtc)
+static int vop_crtc_loader_protect(struct drm_crtc *crtc, bool on)
{
- vop_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
-}
+ struct vop *vop = to_vop(crtc);
-static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
- const struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode)
-{
- if (adjusted_mode->htotal == 0 || adjusted_mode->vtotal == 0)
- return false;
+ if (on == vop->loader_protect)
+ return 0;
- return true;
+ if (on) {
+ vop_power_enable(crtc);
+ enable_irq(vop->irq);
+ drm_crtc_vblank_on(crtc);
+ vop->loader_protect = true;
+ } else {
+ vop_crtc_disable(crtc);
+
+ vop->loader_protect = false;
+ }
+
+ return 0;
}
-static int vop_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
- struct drm_framebuffer *old_fb)
+#define DEBUG_PRINT(args...) \
+ do { \
+ if (s) \
+ seq_printf(s, args); \
+ else \
+ printk(args); \
+ } while (0)
+
+static int vop_plane_info_dump(struct seq_file *s, struct drm_plane *plane)
{
- int ret;
+ struct vop_win *win = to_vop_win(plane);
+ struct drm_plane_state *state = plane->state;
+ struct vop_plane_state *pstate = to_vop_plane_state(state);
+ struct drm_rect *src, *dest;
+ struct drm_framebuffer *fb = state->fb;
+ int i;
- crtc->x = x;
- crtc->y = y;
+ DEBUG_PRINT(" win%d-%d: %s\n", win->win_id, win->area_id,
+ pstate->enable ? "ACTIVE" : "DISABLED");
+ if (!fb)
+ return 0;
- ret = vop_update_primary_plane(crtc, NULL);
- if (ret < 0) {
- DRM_ERROR("fail to update plane\n");
- return ret;
+ src = &pstate->src;
+ dest = &pstate->dest;
+
+ DEBUG_PRINT("\tformat: %s%s\n", drm_get_format_name(fb->pixel_format),
+ fb->modifier[0] == DRM_FORMAT_MOD_ARM_AFBC ? "[AFBC]" : "");
+ DEBUG_PRINT("\tzpos: %d\n", pstate->zpos);
+ DEBUG_PRINT("\tsrc: pos[%dx%d] rect[%dx%d]\n", src->x1 >> 16,
+ src->y1 >> 16, drm_rect_width(src) >> 16,
+ drm_rect_height(src) >> 16);
+ DEBUG_PRINT("\tdst: pos[%dx%d] rect[%dx%d]\n", dest->x1, dest->y1,
+ drm_rect_width(dest), drm_rect_height(dest));
+
+ for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
+ dma_addr_t fb_addr = rockchip_fb_get_dma_addr(fb, i);
+ DEBUG_PRINT("\tbuf[%d]: addr: %pad pitch: %d offset: %d\n",
+ i, &fb_addr, fb->pitches[i], fb->offsets[i]);
}
return 0;
}
-static int vop_crtc_mode_set(struct drm_crtc *crtc,
- struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode,
- int x, int y, struct drm_framebuffer *fb)
+static int vop_crtc_debugfs_dump(struct drm_crtc *crtc, struct seq_file *s)
{
struct vop *vop = to_vop(crtc);
- u16 hsync_len = adjusted_mode->hsync_end - adjusted_mode->hsync_start;
- u16 hdisplay = adjusted_mode->hdisplay;
- u16 htotal = adjusted_mode->htotal;
- u16 hact_st = adjusted_mode->htotal - adjusted_mode->hsync_start;
- u16 hact_end = hact_st + hdisplay;
- u16 vdisplay = adjusted_mode->vdisplay;
- u16 vtotal = adjusted_mode->vtotal;
- u16 vsync_len = adjusted_mode->vsync_end - adjusted_mode->vsync_start;
- u16 vact_st = adjusted_mode->vtotal - adjusted_mode->vsync_start;
- u16 vact_end = vact_st + vdisplay;
- int ret, ret_clk;
- uint32_t val;
+ struct drm_crtc_state *crtc_state = crtc->state;
+ struct drm_display_mode *mode = &crtc->state->adjusted_mode;
+ struct rockchip_crtc_state *state = to_rockchip_crtc_state(crtc->state);
+ bool interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
+ struct drm_plane *plane;
+ int i;
- /*
- * disable dclk to stop frame scan, so that we can safe config mode and
- * enable iommu.
- */
- clk_disable(vop->dclk);
+ DEBUG_PRINT("VOP [%s]: %s\n", dev_name(vop->dev),
+ crtc_state->active ? "ACTIVE" : "DISABLED");
- switch (vop->connector_type) {
- case DRM_MODE_CONNECTOR_LVDS:
- VOP_CTRL_SET(vop, rgb_en, 1);
- break;
- case DRM_MODE_CONNECTOR_eDP:
+ if (!crtc_state->active)
+ return 0;
+
+ DEBUG_PRINT(" Connector: %s\n",
+ drm_get_connector_name(state->output_type));
+ DEBUG_PRINT("\tbus_format[%x] output_mode[%x]\n",
+ state->bus_format, state->output_mode);
+ DEBUG_PRINT(" Display mode: %dx%d%s%d\n",
+ mode->hdisplay, mode->vdisplay, interlaced ? "i" : "p",
+ drm_mode_vrefresh(mode));
+ DEBUG_PRINT("\tclk[%d] real_clk[%d] type[%x] flag[%x]\n",
+ mode->clock, mode->crtc_clock, mode->type, mode->flags);
+ DEBUG_PRINT("\tH: %d %d %d %d\n", mode->hdisplay, mode->hsync_start,
+ mode->hsync_end, mode->htotal);
+ DEBUG_PRINT("\tV: %d %d %d %d\n", mode->vdisplay, mode->vsync_start,
+ mode->vsync_end, mode->vtotal);
+
+ for (i = 0; i < vop->num_wins; i++) {
+ plane = &vop->win[i].base;
+ vop_plane_info_dump(s, plane);
+ }
+
+ return 0;
+}
+
+static void vop_crtc_regs_dump(struct drm_crtc *crtc, struct seq_file *s)
+{
+ struct vop *vop = to_vop(crtc);
+ struct drm_crtc_state *crtc_state = crtc->state;
+ int dump_len = vop->len > 0x400 ? 0x400 : vop->len;
+ int i;
+
+ if (!crtc_state->active)
+ return;
+
+ for (i = 0; i < dump_len; i += 4) {
+ if (i % 16 == 0)
+ DEBUG_PRINT("\n0x%08x: ", i);
+ DEBUG_PRINT("%08x ", vop_readl(vop, i));
+ }
+}
+
+#undef DEBUG_PRINT
+
+static enum drm_mode_status
+vop_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode,
+ int output_type)
+{
+ struct vop *vop = to_vop(crtc);
+ const struct vop_data *vop_data = vop->data;
+ int request_clock = mode->clock;
+ int clock;
+
+ if (mode->hdisplay > vop_data->max_output.width)
+ return MODE_BAD_HVALUE;
+
+ if ((mode->flags & DRM_MODE_FLAG_INTERLACE) &&
+ VOP_MAJOR(vop->data->version) == 3 &&
+ VOP_MINOR(vop->data->version) <= 2)
+ return MODE_BAD;
+
+ if (mode->flags & DRM_MODE_FLAG_DBLCLK)
+ request_clock *= 2;
+ clock = clk_round_rate(vop->dclk, request_clock * 1000) / 1000;
+
+ /*
+ * Hdmi or DisplayPort request a Accurate clock.
+ */
+ if (output_type == DRM_MODE_CONNECTOR_HDMIA ||
+ output_type == DRM_MODE_CONNECTOR_DisplayPort)
+ if (clock != request_clock)
+ return MODE_CLOCK_RANGE;
+
+ return MODE_OK;
+}
+
+static const struct rockchip_crtc_funcs private_crtc_funcs = {
+ .loader_protect = vop_crtc_loader_protect,
+ .enable_vblank = vop_crtc_enable_vblank,
+ .disable_vblank = vop_crtc_disable_vblank,
+ .cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
+ .debugfs_dump = vop_crtc_debugfs_dump,
+ .regs_dump = vop_crtc_regs_dump,
+ .mode_valid = vop_crtc_mode_valid,
+};
+
+static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
+ const struct drm_display_mode *mode,
+ struct drm_display_mode *adj_mode)
+{
+ struct vop *vop = to_vop(crtc);
+ const struct vop_data *vop_data = vop->data;
+
+ if (mode->hdisplay > vop_data->max_output.width)
+ return false;
+
+ drm_mode_set_crtcinfo(adj_mode,
+ CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE);
+
+ if (mode->flags & DRM_MODE_FLAG_DBLCLK)
+ adj_mode->crtc_clock *= 2;
+
+ adj_mode->crtc_clock =
+ clk_round_rate(vop->dclk, adj_mode->crtc_clock * 1000) / 1000;
+
+ return true;
+}
+
+static void vop_crtc_enable(struct drm_crtc *crtc)
+{
+ struct vop *vop = to_vop(crtc);
+ const struct vop_data *vop_data = vop->data;
+ struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
+ struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
+ u16 hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
+ u16 hdisplay = adjusted_mode->crtc_hdisplay;
+ u16 htotal = adjusted_mode->crtc_htotal;
+ u16 hact_st = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_start;
+ u16 hact_end = hact_st + hdisplay;
+ u16 vdisplay = adjusted_mode->crtc_vdisplay;
+ u16 vtotal = adjusted_mode->crtc_vtotal;
+ u16 vsync_len = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
+ u16 vact_st = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start;
+ u16 vact_end = vact_st + vdisplay;
+ uint32_t val;
+
+ mutex_lock(&vop->vop_lock);
+ vop_initial(crtc);
+
+ VOP_CTRL_SET(vop, dclk_pol, 1);
+ val = (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ?
+ 0 : BIT(HSYNC_POSITIVE);
+ val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ?
+ 0 : BIT(VSYNC_POSITIVE);
+ VOP_CTRL_SET(vop, pin_pol, val);
+
+ if (vop->dclk_source && s->pll && s->pll->pll) {
+ if (clk_set_parent(vop->dclk_source, s->pll->pll))
+ DRM_DEV_ERROR(vop->dev,
+ "failed to set dclk's parents\n");
+ }
+
+ switch (s->output_type) {
+ case DRM_MODE_CONNECTOR_LVDS:
+ VOP_CTRL_SET(vop, rgb_en, 1);
+ VOP_CTRL_SET(vop, rgb_pin_pol, val);
+ VOP_CTRL_SET(vop, rgb_dclk_pol, 1);
+ VOP_CTRL_SET(vop, lvds_en, 1);
+ VOP_CTRL_SET(vop, lvds_pin_pol, val);
+ VOP_CTRL_SET(vop, lvds_dclk_pol, 1);
+ break;
+ case DRM_MODE_CONNECTOR_eDP:
VOP_CTRL_SET(vop, edp_en, 1);
+ VOP_CTRL_SET(vop, edp_pin_pol, val);
+ VOP_CTRL_SET(vop, edp_dclk_pol, 1);
break;
case DRM_MODE_CONNECTOR_HDMIA:
VOP_CTRL_SET(vop, hdmi_en, 1);
+ VOP_CTRL_SET(vop, hdmi_pin_pol, val);
+ VOP_CTRL_SET(vop, hdmi_dclk_pol, 1);
+ break;
+ case DRM_MODE_CONNECTOR_DSI:
+ VOP_CTRL_SET(vop, mipi_en, 1);
+ VOP_CTRL_SET(vop, mipi_pin_pol, val);
+ VOP_CTRL_SET(vop, mipi_dclk_pol, 1);
+ break;
+ case DRM_MODE_CONNECTOR_DisplayPort:
+ VOP_CTRL_SET(vop, dp_dclk_pol, 0);
+ VOP_CTRL_SET(vop, dp_pin_pol, val);
+ VOP_CTRL_SET(vop, dp_en, 1);
+ break;
+ case DRM_MODE_CONNECTOR_TV:
+ if (vdisplay == CVBS_PAL_VDISPLAY)
+ VOP_CTRL_SET(vop, tve_sw_mode, 1);
+ else
+ VOP_CTRL_SET(vop, tve_sw_mode, 0);
+
+ VOP_CTRL_SET(vop, tve_dclk_pol, 1);
+ VOP_CTRL_SET(vop, tve_dclk_en, 1);
+ /* use the same pol reg with hdmi */
+ VOP_CTRL_SET(vop, hdmi_pin_pol, val);
+ VOP_CTRL_SET(vop, sw_genlock, 1);
+ VOP_CTRL_SET(vop, sw_uv_offset_en, 1);
+ VOP_CTRL_SET(vop, dither_up, 1);
break;
default:
- DRM_ERROR("unsupport connector_type[%d]\n",
- vop->connector_type);
- ret = -EINVAL;
- goto out;
- };
- VOP_CTRL_SET(vop, out_mode, vop->connector_out_mode);
+ DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
+ }
- val = 0x8;
- val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
- val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
- VOP_CTRL_SET(vop, pin_pol, val);
+ if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
+ !(vop_data->feature & VOP_FEATURE_OUTPUT_10BIT))
+ s->output_mode = ROCKCHIP_OUT_MODE_P888;
+ VOP_CTRL_SET(vop, out_mode, s->output_mode);
+ switch (s->bus_format) {
+ case MEDIA_BUS_FMT_RGB565_1X16:
+ val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB565);
+ break;
+ case MEDIA_BUS_FMT_RGB666_1X18:
+ case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
+ val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB666);
+ break;
+ case MEDIA_BUS_FMT_YUV8_1X24:
+ case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
+ val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(1);
+ break;
+ case MEDIA_BUS_FMT_YUV10_1X30:
+ case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
+ val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
+ break;
+ case MEDIA_BUS_FMT_RGB888_1X24:
+ default:
+ val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
+ break;
+ }
+
+ if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA)
+ val |= PRE_DITHER_DOWN_EN(0);
+ else
+ val |= PRE_DITHER_DOWN_EN(1);
+ val |= DITHER_DOWN_MODE_SEL(DITHER_DOWN_ALLEGRO);
+ VOP_CTRL_SET(vop, dither_down, val);
+ VOP_CTRL_SET(vop, dclk_ddr,
+ s->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0);
+ VOP_CTRL_SET(vop, overlay_mode, is_yuv_output(s->bus_format));
+ VOP_CTRL_SET(vop, dsp_out_yuv, is_yuv_output(s->bus_format));
+
+ /*
+ * Background color is 10bit depth if vop version >= 3.5
+ */
+ if (!is_yuv_output(s->bus_format))
+ val = 0;
+ else if (VOP_MAJOR(vop->data->version) == 3 &&
+ VOP_MINOR(vop->data->version) >= 5)
+ val = 0x20010200;
+ else
+ val = 0x801080;
+ VOP_CTRL_SET(vop, dsp_background, val);
VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
val = hact_st << 16;
val |= hact_end;
VOP_CTRL_SET(vop, hact_st_end, val);
VOP_CTRL_SET(vop, hpost_st_end, val);
- VOP_CTRL_SET(vop, vtotal_pw, (vtotal << 16) | vsync_len);
val = vact_st << 16;
val |= vact_end;
VOP_CTRL_SET(vop, vact_st_end, val);
VOP_CTRL_SET(vop, vpost_st_end, val);
- ret = vop_crtc_mode_set_base(crtc, x, y, fb);
- if (ret)
- goto out;
+ VOP_INTR_SET(vop, line_flag_num[0], vact_end);
+ VOP_INTR_SET(vop, line_flag_num[1],
+ vact_end - us_to_vertical_line(adjusted_mode, 1000));
+ if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
+ u16 vact_st_f1 = vtotal + vact_st + 1;
+ u16 vact_end_f1 = vact_st_f1 + vdisplay;
+
+ val = vact_st_f1 << 16 | vact_end_f1;
+ VOP_CTRL_SET(vop, vact_st_end_f1, val);
+ VOP_CTRL_SET(vop, vpost_st_end_f1, val);
+
+ val = vtotal << 16 | (vtotal + vsync_len);
+ VOP_CTRL_SET(vop, vs_st_end_f1, val);
+ VOP_CTRL_SET(vop, dsp_interlace, 1);
+ VOP_CTRL_SET(vop, p2i_en, 1);
+ vtotal += vtotal + 1;
+ } else {
+ VOP_CTRL_SET(vop, dsp_interlace, 0);
+ VOP_CTRL_SET(vop, p2i_en, 0);
+ }
+ VOP_CTRL_SET(vop, vtotal_pw, vtotal << 16 | vsync_len);
+
+ VOP_CTRL_SET(vop, core_dclk_div,
+ !!(adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK));
+
+ VOP_CTRL_SET(vop, cabc_total_num, hdisplay * vdisplay);
+ VOP_CTRL_SET(vop, cabc_config_mode, STAGE_BY_STAGE);
+ VOP_CTRL_SET(vop, cabc_stage_up_mode, MUL_MODE);
+ VOP_CTRL_SET(vop, cabc_scale_cfg_value, 1);
+ VOP_CTRL_SET(vop, cabc_scale_cfg_enable, 0);
+ VOP_CTRL_SET(vop, cabc_global_dn_limit_en, 1);
+ clk_set_rate(vop->dclk, adjusted_mode->crtc_clock * 1000);
+
+ vop_cfg_done(vop);
/*
- * reset dclk, take all mode config affect, so the clk would run in
- * correct frame.
+ * enable vop, all the register would take effect when vop exit standby
*/
- reset_control_assert(vop->dclk_rst);
- usleep_range(10, 20);
- reset_control_deassert(vop->dclk_rst);
+ VOP_CTRL_SET(vop, standby, 0);
- clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
-out:
- ret_clk = clk_enable(vop->dclk);
- if (ret_clk < 0) {
- dev_err(vop->dev, "failed to enable dclk - %d\n", ret_clk);
- return ret_clk;
+ enable_irq(vop->irq);
+ drm_crtc_vblank_on(crtc);
+ mutex_unlock(&vop->vop_lock);
+}
+
+static int vop_zpos_cmp(const void *a, const void *b)
+{
+ struct vop_zpos *pa = (struct vop_zpos *)a;
+ struct vop_zpos *pb = (struct vop_zpos *)b;
+
+ return pa->zpos - pb->zpos;
+}
+
+static int vop_afbdc_atomic_check(struct drm_crtc *crtc,
+ struct drm_crtc_state *crtc_state)
+{
+ struct vop *vop = to_vop(crtc);
+ const struct vop_data *vop_data = vop->data;
+ struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
+ struct drm_atomic_state *state = crtc_state->state;
+ struct drm_plane *plane;
+ struct drm_plane_state *pstate;
+ struct vop_plane_state *plane_state;
+ struct vop_win *win;
+ int afbdc_format;
+ int i;
+
+ s->afbdc_en = 0;
+
+ for_each_plane_in_state(state, plane, pstate, i) {
+ struct drm_framebuffer *fb = pstate->fb;
+ struct drm_rect *src;
+
+ win = to_vop_win(plane);
+ plane_state = to_vop_plane_state(pstate);
+
+ if (pstate->crtc != crtc || !fb)
+ continue;
+
+ if (fb->modifier[0] != DRM_FORMAT_MOD_ARM_AFBC)
+ continue;
+
+ if (!(vop_data->feature & VOP_FEATURE_AFBDC)) {
+ DRM_ERROR("not support afbdc\n");
+ return -EINVAL;
+ }
+
+ switch (plane_state->format) {
+ case VOP_FMT_ARGB8888:
+ afbdc_format = AFBDC_FMT_U8U8U8U8;
+ break;
+ case VOP_FMT_RGB888:
+ afbdc_format = AFBDC_FMT_U8U8U8;
+ break;
+ case VOP_FMT_RGB565:
+ afbdc_format = AFBDC_FMT_RGB565;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (s->afbdc_en) {
+ DRM_ERROR("vop only support one afbc layer\n");
+ return -EINVAL;
+ }
+
+ src = &plane_state->src;
+ if (src->x1 || src->y1 || fb->offsets[0]) {
+ DRM_ERROR("win[%d] afbdc not support offset display\n",
+ win->win_id);
+ DRM_ERROR("xpos=%d, ypos=%d, offset=%d\n",
+ src->x1, src->y1, fb->offsets[0]);
+ return -EINVAL;
+ }
+ s->afbdc_win_format = afbdc_format;
+ s->afbdc_win_width = pstate->fb->width - 1;
+ s->afbdc_win_height = (drm_rect_height(src) >> 16) - 1;
+ s->afbdc_win_id = win->win_id;
+ s->afbdc_win_ptr = plane_state->yrgb_mst;
+ s->afbdc_en = 1;
}
+ return 0;
+}
+
+static void vop_dclk_source_generate(struct drm_crtc *crtc,
+ struct drm_crtc_state *crtc_state)
+{
+ struct rockchip_drm_private *private = crtc->dev->dev_private;
+ struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
+ struct rockchip_crtc_state *old_s = to_rockchip_crtc_state(crtc->state);
+ struct vop *vop = to_vop(crtc);
+
+ if (!vop->dclk_source)
+ return;
+
+ if (crtc_state->active) {
+ WARN_ON(s->pll && !s->pll->use_count);
+ if (!s->pll || s->pll->use_count > 1 ||
+ s->output_type != old_s->output_type) {
+ if (s->pll)
+ s->pll->use_count--;
+
+ if (s->output_type != DRM_MODE_CONNECTOR_HDMIA &&
+ !private->default_pll.use_count)
+ s->pll = &private->default_pll;
+ else
+ s->pll = &private->hdmi_pll;
+
+ s->pll->use_count++;
+ }
+ } else if (s->pll) {
+ s->pll->use_count--;
+ s->pll = NULL;
+ }
+ if (s->pll && s->pll != old_s->pll)
+ crtc_state->mode_changed = true;
+}
+
+static int vop_crtc_atomic_check(struct drm_crtc *crtc,
+ struct drm_crtc_state *crtc_state)
+{
+ struct drm_atomic_state *state = crtc_state->state;
+ struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
+ struct vop *vop = to_vop(crtc);
+ const struct vop_data *vop_data = vop->data;
+ struct drm_plane *plane;
+ struct drm_plane_state *pstate;
+ struct vop_plane_state *plane_state;
+ struct vop_zpos *pzpos;
+ int dsp_layer_sel = 0;
+ int i, j, cnt = 0, ret = 0;
+
+ ret = vop_afbdc_atomic_check(crtc, crtc_state);
+ if (ret)
+ return ret;
+
+ ret = vop_csc_atomic_check(crtc, crtc_state);
+ if (ret)
+ return ret;
+
+ pzpos = kmalloc_array(vop_data->win_size, sizeof(*pzpos), GFP_KERNEL);
+ if (!pzpos)
+ return -ENOMEM;
+
+ for (i = 0; i < vop_data->win_size; i++) {
+ const struct vop_win_data *win_data = &vop_data->win[i];
+ struct vop_win *win;
+
+ if (!win_data->phy)
+ continue;
+
+ for (j = 0; j < vop->num_wins; j++) {
+ win = &vop->win[j];
+
+ if (win->win_id == i && !win->area_id)
+ break;
+ }
+ if (WARN_ON(j >= vop->num_wins)) {
+ ret = -EINVAL;
+ goto err_free_pzpos;
+ }
+
+ plane = &win->base;
+ pstate = state->plane_states[drm_plane_index(plane)];
+ /*
+ * plane might not have changed, in which case take
+ * current state:
+ */
+ if (!pstate)
+ pstate = plane->state;
+ plane_state = to_vop_plane_state(pstate);
+ pzpos[cnt].zpos = plane_state->zpos;
+ pzpos[cnt++].win_id = win->win_id;
+ }
+
+ sort(pzpos, cnt, sizeof(pzpos[0]), vop_zpos_cmp, NULL);
+
+ for (i = 0, cnt = 0; i < vop_data->win_size; i++) {
+ const struct vop_win_data *win_data = &vop_data->win[i];
+ int shift = i * 2;
+
+ if (win_data->phy) {
+ struct vop_zpos *zpos = &pzpos[cnt++];
+
+ dsp_layer_sel |= zpos->win_id << shift;
+ } else {
+ dsp_layer_sel |= i << shift;
+ }
+ }
+
+ s->dsp_layer_sel = dsp_layer_sel;
+
+ vop_dclk_source_generate(crtc, crtc_state);
+
+err_free_pzpos:
+ kfree(pzpos);
return ret;
}
-static void vop_crtc_commit(struct drm_crtc *crtc)
+static void vop_post_config(struct drm_crtc *crtc)
+{
+ struct vop *vop = to_vop(crtc);
+ struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
+ struct drm_display_mode *mode = &crtc->state->adjusted_mode;
+ u16 vtotal = mode->crtc_vtotal;
+ u16 hdisplay = mode->crtc_hdisplay;
+ u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start;
+ u16 vdisplay = mode->crtc_vdisplay;
+ u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start;
+ u16 hsize = hdisplay * (s->left_margin + s->right_margin) / 200;
+ u16 vsize = vdisplay * (s->top_margin + s->bottom_margin) / 200;
+ u16 hact_end, vact_end;
+ u32 val;
+
+ hact_st += hdisplay * (100 - s->left_margin) / 200;
+ hact_end = hact_st + hsize;
+ val = hact_st << 16;
+ val |= hact_end;
+ VOP_CTRL_SET(vop, hpost_st_end, val);
+ vact_st += vdisplay * (100 - s->top_margin) / 200;
+ vact_end = vact_st + vsize;
+ val = vact_st << 16;
+ val |= vact_end;
+ VOP_CTRL_SET(vop, vpost_st_end, val);
+ val = scl_cal_scale2(vdisplay, vsize) << 16;
+ val |= scl_cal_scale2(hdisplay, hsize);
+ VOP_CTRL_SET(vop, post_scl_factor, val);
+
+#define POST_HORIZONTAL_SCALEDOWN_EN(x) ((x) << 0)
+#define POST_VERTICAL_SCALEDOWN_EN(x) ((x) << 1)
+ VOP_CTRL_SET(vop, post_scl_ctrl,
+ POST_HORIZONTAL_SCALEDOWN_EN(hdisplay != hsize) ||
+ POST_VERTICAL_SCALEDOWN_EN(vdisplay != vsize));
+ if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
+ u16 vact_st_f1 = vtotal + vact_st + 1;
+ u16 vact_end_f1 = vact_st_f1 + vsize;
+
+ val = vact_st_f1 << 16 | vact_end_f1;
+ VOP_CTRL_SET(vop, vpost_st_end_f1, val);
+ }
+}
+
+static void vop_update_cabc_lut(struct drm_crtc *crtc,
+ struct drm_crtc_state *old_crtc_state)
+{
+ struct rockchip_crtc_state *s =
+ to_rockchip_crtc_state(crtc->state);
+ struct rockchip_crtc_state *old_s =
+ to_rockchip_crtc_state(old_crtc_state);
+ struct drm_property_blob *cabc_lut = s->cabc_lut;
+ struct drm_property_blob *old_cabc_lut = old_s->cabc_lut;
+ struct vop *vop = to_vop(crtc);
+ int lut_size;
+ u32 *lut;
+ u32 lut_len = vop->cabc_lut_len;
+ int i, dle;
+
+ if (!cabc_lut && old_cabc_lut) {
+ VOP_CTRL_SET(vop, cabc_lut_en, 0);
+ return;
+ }
+ if (!cabc_lut)
+ return;
+
+ if (old_cabc_lut && old_cabc_lut->base.id == cabc_lut->base.id)
+ return;
+
+ lut = (u32 *)cabc_lut->data;
+ lut_size = cabc_lut->length / sizeof(u32);
+ if (WARN(lut_size != lut_len, "Unexpect cabc lut size not match\n"))
+ return;
+
+#define CTRL_GET(name) VOP_CTRL_GET(vop, name)
+ if (CTRL_GET(cabc_lut_en)) {
+ VOP_CTRL_SET(vop, cabc_lut_en, 0);
+ vop_cfg_done(vop);
+ readx_poll_timeout(CTRL_GET, cabc_lut_en, dle, !dle, 5, 33333);
+ }
+
+ for (i = 0; i < lut_len; i++)
+ vop_write_cabc_lut(vop, (i << 2), lut[i]);
+#undef CTRL_GET
+ VOP_CTRL_SET(vop, cabc_lut_en, 1);
+}
+
+static void vop_update_cabc(struct drm_crtc *crtc,
+ struct drm_crtc_state *old_crtc_state)
+{
+ struct rockchip_crtc_state *s =
+ to_rockchip_crtc_state(crtc->state);
+ struct vop *vop = to_vop(crtc);
+ struct drm_display_mode *mode = &crtc->state->adjusted_mode;
+ int pixel_total = mode->hdisplay * mode->vdisplay;
+
+ if (!vop->cabc_lut_regs)
+ return;
+
+ vop_update_cabc_lut(crtc, old_crtc_state);
+
+ if (s->cabc_mode != ROCKCHIP_DRM_CABC_MODE_DISABLE) {
+ VOP_CTRL_SET(vop, cabc_en, 1);
+ VOP_CTRL_SET(vop, cabc_handle_en, 1);
+ VOP_CTRL_SET(vop, cabc_stage_up, s->cabc_stage_up);
+ VOP_CTRL_SET(vop, cabc_stage_down, s->cabc_stage_down);
+ VOP_CTRL_SET(vop, cabc_global_dn, s->cabc_global_dn);
+ VOP_CTRL_SET(vop, cabc_calc_pixel_num,
+ s->cabc_calc_pixel_num * pixel_total / 1000);
+ } else {
+ /*
+ * There are some hardware issues on cabc disabling:
+ * 1: if cabc auto gating enable, cabc disabling will cause
+ * vop die
+ * 2: cabc disabling always would make timing several
+ * pixel cycle abnormal, cause some panel abnormal.
+ *
+ * So just keep cabc enable, and make it no work with max
+ * cabc_calc_pixel_num, it only has little power consume.
+ */
+ VOP_CTRL_SET(vop, cabc_calc_pixel_num, pixel_total);
+ }
+}
+
+static void vop_cfg_update(struct drm_crtc *crtc,
+ struct drm_crtc_state *old_crtc_state)
+{
+ struct rockchip_crtc_state *s =
+ to_rockchip_crtc_state(crtc->state);
+ struct vop *vop = to_vop(crtc);
+
+ spin_lock(&vop->reg_lock);
+
+ if (s->afbdc_en) {
+ uint32_t pic_size;
+
+ VOP_CTRL_SET(vop, afbdc_format, s->afbdc_win_format | 1 << 4);
+ VOP_CTRL_SET(vop, afbdc_hreg_block_split, 0);
+ VOP_CTRL_SET(vop, afbdc_sel, s->afbdc_win_id);
+ VOP_CTRL_SET(vop, afbdc_hdr_ptr, s->afbdc_win_ptr);
+ pic_size = (s->afbdc_win_width & 0xffff);
+ pic_size |= s->afbdc_win_height << 16;
+ VOP_CTRL_SET(vop, afbdc_pic_size, pic_size);
+ }
+
+ VOP_CTRL_SET(vop, afbdc_en, s->afbdc_en);
+ VOP_CTRL_SET(vop, dsp_layer_sel, s->dsp_layer_sel);
+ vop_post_config(crtc);
+
+ spin_unlock(&vop->reg_lock);
+}
+
+static bool vop_fs_irq_is_pending(struct vop *vop)
+{
+ return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
+}
+
+static void vop_wait_for_irq_handler(struct vop *vop)
+{
+ bool pending;
+ int ret;
+
+ /*
+ * Spin until frame start interrupt status bit goes low, which means
+ * that interrupt handler was invoked and cleared it. The timeout of
+ * 10 msecs is really too long, but it is just a safety measure if
+ * something goes really wrong. The wait will only happen in the very
+ * unlikely case of a vblank happening exactly at the same time and
+ * shouldn't exceed microseconds range.
+ */
+ ret = readx_poll_timeout_atomic(vop_fs_irq_is_pending, vop, pending,
+ !pending, 0, 10 * 1000);
+ if (ret)
+ DRM_DEV_ERROR(vop->dev, "VOP vblank IRQ stuck for 10 ms\n");
+
+ synchronize_irq(vop->irq);
+}
+
+static void vop_crtc_atomic_flush(struct drm_crtc *crtc,
+ struct drm_crtc_state *old_crtc_state)
+{
+ struct drm_atomic_state *old_state = old_crtc_state->state;
+ struct drm_plane_state *old_plane_state;
+ struct vop *vop = to_vop(crtc);
+ struct drm_plane *plane;
+ int i;
+
+ vop_cfg_update(crtc, old_crtc_state);
+
+ if (!vop->is_iommu_enabled && vop->is_iommu_needed) {
+ bool need_wait_vblank = !vop_is_allwin_disabled(vop);
+ int ret;
+
+ if (need_wait_vblank) {
+ bool active;
+
+ disable_irq(vop->irq);
+ drm_crtc_vblank_get(crtc);
+ VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
+
+ ret = readx_poll_timeout_atomic(vop_fs_irq_is_active,
+ vop, active, active,
+ 0, 50 * 1000);
+ if (ret)
+ dev_err(vop->dev, "wait fs irq timeout\n");
+
+ VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
+ vop_cfg_done(vop);
+
+ ret = readx_poll_timeout_atomic(vop_line_flag_is_active,
+ vop, active, active,
+ 0, 50 * 1000);
+ if (ret)
+ dev_err(vop->dev, "wait line flag timeout\n");
+
+ enable_irq(vop->irq);
+ }
+ ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
+ if (ret)
+ dev_err(vop->dev, "failed to attach dma mapping, %d\n",
+ ret);
+
+ if (need_wait_vblank) {
+ VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
+ drm_crtc_vblank_put(crtc);
+ }
+
+ vop->is_iommu_enabled = true;
+ }
+
+ vop_update_cabc(crtc, old_crtc_state);
+
+ vop_cfg_done(vop);
+
+ /*
+ * There is a (rather unlikely) possiblity that a vblank interrupt
+ * fired before we set the cfg_done bit. To avoid spuriously
+ * signalling flip completion we need to wait for it to finish.
+ */
+ vop_wait_for_irq_handler(vop);
+
+ for_each_plane_in_state(old_state, plane, old_plane_state, i) {
+ if (!old_plane_state->fb)
+ continue;
+
+ if (old_plane_state->fb == plane->state->fb)
+ continue;
+
+ drm_framebuffer_reference(old_plane_state->fb);
+ drm_flip_work_queue(&vop->fb_unref_work, old_plane_state->fb);
+ set_bit(VOP_PENDING_FB_UNREF, &vop->pending);
+ WARN_ON(drm_crtc_vblank_get(crtc) != 0);
+ }
+}
+
+static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
+ struct drm_crtc_state *old_crtc_state)
{
+ struct vop *vop = to_vop(crtc);
+
+ if (crtc->state->event) {
+ WARN_ON(drm_crtc_vblank_get(crtc) != 0);
+
+ vop->event = crtc->state->event;
+ crtc->state->event = NULL;
+ }
}
static const struct drm_crtc_helper_funcs vop_crtc_helper_funcs = {
- .dpms = vop_crtc_dpms,
- .prepare = vop_crtc_prepare,
+ .load_lut = vop_crtc_load_lut,
+ .enable = vop_crtc_enable,
+ .disable = vop_crtc_disable,
.mode_fixup = vop_crtc_mode_fixup,
- .mode_set = vop_crtc_mode_set,
- .mode_set_base = vop_crtc_mode_set_base,
- .commit = vop_crtc_commit,
+ .atomic_check = vop_crtc_atomic_check,
+ .atomic_flush = vop_crtc_atomic_flush,
+ .atomic_begin = vop_crtc_atomic_begin,
};
-static int vop_crtc_page_flip(struct drm_crtc *crtc,
- struct drm_framebuffer *fb,
- struct drm_pending_vblank_event *event,
- uint32_t page_flip_flags)
+static void vop_crtc_destroy(struct drm_crtc *crtc)
+{
+ drm_crtc_cleanup(crtc);
+}
+
+static void vop_crtc_reset(struct drm_crtc *crtc)
{
+ struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
+ struct rockchip_drm_private *private = crtc->dev->dev_private;
struct vop *vop = to_vop(crtc);
- struct drm_framebuffer *old_fb = crtc->primary->fb;
- int ret;
- /* when the page flip is requested, crtc should be on */
- if (!vop->is_enabled) {
- DRM_DEBUG("page flip request rejected because crtc is off.\n");
- return 0;
+ if (crtc->state) {
+ __drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
+ kfree(s);
}
- crtc->primary->fb = fb;
+ s = kzalloc(sizeof(*s), GFP_KERNEL);
+ if (!s)
+ return;
+ crtc->state = &s->base;
+ crtc->state->crtc = crtc;
+
+ if (vop->dclk_source) {
+ struct clk *parent;
+
+ parent = clk_get_parent(vop->dclk_source);
+ if (parent) {
+ if (clk_is_match(private->default_pll.pll, parent))
+ s->pll = &private->default_pll;
+ else if (clk_is_match(private->hdmi_pll.pll, parent))
+ s->pll = &private->hdmi_pll;
+ if (s->pll)
+ s->pll->use_count++;
+ }
+ }
+ s->left_margin = 100;
+ s->right_margin = 100;
+ s->top_margin = 100;
+ s->bottom_margin = 100;
+}
- ret = vop_update_primary_plane(crtc, event);
- if (ret)
- crtc->primary->fb = old_fb;
+static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
+{
+ struct rockchip_crtc_state *rockchip_state, *old_state;
- return ret;
+ old_state = to_rockchip_crtc_state(crtc->state);
+ rockchip_state = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL);
+ if (!rockchip_state)
+ return NULL;
+
+ __drm_atomic_helper_crtc_duplicate_state(crtc, &rockchip_state->base);
+ return &rockchip_state->base;
}
-static void vop_win_state_complete(struct vop_win *vop_win,
- struct vop_win_state *state)
+static void vop_crtc_destroy_state(struct drm_crtc *crtc,
+ struct drm_crtc_state *state)
{
- struct vop *vop = vop_win->vop;
- struct drm_crtc *crtc = &vop->crtc;
- struct drm_device *drm = crtc->dev;
- unsigned long flags;
+ struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
+
+ __drm_atomic_helper_crtc_destroy_state(crtc, &s->base);
+ kfree(s);
+}
+
+static int vop_crtc_atomic_get_property(struct drm_crtc *crtc,
+ const struct drm_crtc_state *state,
+ struct drm_property *property,
+ uint64_t *val)
+{
+ struct drm_device *drm_dev = crtc->dev;
+ struct rockchip_drm_private *private = drm_dev->dev_private;
+ struct drm_mode_config *mode_config = &drm_dev->mode_config;
+ struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
+
+ if (property == mode_config->tv_left_margin_property) {
+ *val = s->left_margin;
+ return 0;
+ }
+
+ if (property == mode_config->tv_right_margin_property) {
+ *val = s->right_margin;
+ return 0;
+ }
+
+ if (property == mode_config->tv_top_margin_property) {
+ *val = s->top_margin;
+ return 0;
+ }
+
+ if (property == mode_config->tv_bottom_margin_property) {
+ *val = s->bottom_margin;
+ return 0;
+ }
+
+ if (property == private->cabc_mode_property) {
+ *val = s->cabc_mode;
+ return 0;
+ }
+
+ if (property == private->cabc_stage_up_property) {
+ *val = s->cabc_stage_up;
+ return 0;
+ }
+
+ if (property == private->cabc_stage_down_property) {
+ *val = s->cabc_stage_down;
+ return 0;
+ }
+
+ if (property == private->cabc_global_dn_property) {
+ *val = s->cabc_global_dn;
+ return 0;
+ }
+
+ if (property == private->cabc_calc_pixel_num_property) {
+ *val = s->cabc_calc_pixel_num;
+ return 0;
+ }
- if (state->event) {
- spin_lock_irqsave(&drm->event_lock, flags);
- drm_crtc_send_vblank_event(crtc, state->event);
- spin_unlock_irqrestore(&drm->event_lock, flags);
+ if (property == private->cabc_lut_property) {
+ *val = s->cabc_lut ? s->cabc_lut->base.id : 0;
+ return 0;
}
- list_del(&state->head);
- drm_vblank_put(crtc->dev, vop->pipe);
+ DRM_ERROR("failed to get vop crtc property\n");
+ return -EINVAL;
}
-static void vop_crtc_destroy(struct drm_crtc *crtc)
+static int vop_crtc_atomic_set_property(struct drm_crtc *crtc,
+ struct drm_crtc_state *state,
+ struct drm_property *property,
+ uint64_t val)
{
- drm_crtc_cleanup(crtc);
-}
+ struct drm_device *drm_dev = crtc->dev;
+ struct rockchip_drm_private *private = drm_dev->dev_private;
+ struct drm_mode_config *mode_config = &drm_dev->mode_config;
+ struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
+ struct vop *vop = to_vop(crtc);
-static const struct drm_crtc_funcs vop_crtc_funcs = {
- .set_config = drm_crtc_helper_set_config,
- .page_flip = vop_crtc_page_flip,
- .destroy = vop_crtc_destroy,
-};
+ if (property == mode_config->tv_left_margin_property) {
+ s->left_margin = val;
+ return 0;
+ }
-static bool vop_win_state_is_active(struct vop_win *vop_win,
- struct vop_win_state *state)
-{
- bool active = false;
+ if (property == mode_config->tv_right_margin_property) {
+ s->right_margin = val;
+ return 0;
+ }
- if (state->fb) {
- dma_addr_t yrgb_mst;
+ if (property == mode_config->tv_top_margin_property) {
+ s->top_margin = val;
+ return 0;
+ }
- /* check yrgb_mst to tell if pending_fb is now front */
- yrgb_mst = VOP_WIN_GET_YRGBADDR(vop_win->vop, vop_win->data);
+ if (property == mode_config->tv_bottom_margin_property) {
+ s->bottom_margin = val;
+ return 0;
+ }
- active = (yrgb_mst == state->yrgb_mst);
- } else {
- bool enabled;
+ if (property == private->cabc_mode_property) {
+ s->cabc_mode = val;
+ /*
+ * Pre-define lowpower and normal mode to make cabc
+ * easier to use.
+ */
+ if (s->cabc_mode == ROCKCHIP_DRM_CABC_MODE_NORMAL) {
+ s->cabc_stage_up = 257;
+ s->cabc_stage_down = 255;
+ s->cabc_global_dn = 192;
+ s->cabc_calc_pixel_num = 995;
+ } else if (s->cabc_mode == ROCKCHIP_DRM_CABC_MODE_LOWPOWER) {
+ s->cabc_stage_up = 260;
+ s->cabc_stage_down = 252;
+ s->cabc_global_dn = 180;
+ s->cabc_calc_pixel_num = 992;
+ }
+ return 0;
+ }
- /* if enable bit is clear, plane is now disabled */
- enabled = VOP_WIN_GET(vop_win->vop, vop_win->data, enable);
+ if (property == private->cabc_stage_up_property) {
+ s->cabc_stage_up = val;
+ return 0;
+ }
- active = (enabled == 0);
+ if (property == private->cabc_stage_down_property) {
+ s->cabc_stage_down = val;
+ return 0;
}
- return active;
-}
+ if (property == private->cabc_calc_pixel_num_property) {
+ s->cabc_calc_pixel_num = val;
+ return 0;
+ }
-static void vop_win_state_destroy(struct vop_win_state *state)
-{
- struct drm_framebuffer *fb = state->fb;
+ if (property == private->cabc_global_dn_property) {
+ s->cabc_global_dn = val;
+ return 0;
+ }
+
+ if (property == private->cabc_lut_property) {
+ bool replaced;
+ ssize_t size = vop->cabc_lut_len * 4;
- if (fb)
- drm_framebuffer_unreference(fb);
+ return drm_atomic_replace_property_blob_from_id(crtc,
+ &s->cabc_lut,
+ val,
+ size,
+ &replaced);
+ }
- kfree(state);
+ DRM_ERROR("failed to set vop crtc property\n");
+ return -EINVAL;
}
-static void vop_win_update_state(struct vop_win *vop_win)
+static void vop_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
+ u16 *blue, uint32_t start, uint32_t size)
{
- struct vop_win_state *state, *n, *new_active = NULL;
-
- /* Check if any pending states are now active */
- list_for_each_entry(state, &vop_win->pending, head)
- if (vop_win_state_is_active(vop_win, state)) {
- new_active = state;
- break;
- }
+ struct vop *vop = to_vop(crtc);
+ int end = min_t(u32, start + size, vop->lut_len);
+ int i;
- if (!new_active)
+ if (!vop->lut)
return;
- /*
- * Destroy any 'skipped' pending states - states that were queued
- * before the newly active state.
- */
- list_for_each_entry_safe(state, n, &vop_win->pending, head) {
- if (state == new_active)
- break;
- vop_win_state_complete(vop_win, state);
- vop_win_state_destroy(state);
- }
-
- vop_win_state_complete(vop_win, new_active);
+ for (i = start; i < end; i++)
+ rockchip_vop_crtc_fb_gamma_set(crtc, red[i], green[i],
+ blue[i], i);
- if (vop_win->active)
- vop_win_state_destroy(vop_win->active);
- vop_win->active = new_active;
+ vop_crtc_load_lut(crtc);
}
-static bool vop_win_has_pending_state(struct vop_win *vop_win)
+static const struct drm_crtc_funcs vop_crtc_funcs = {
+ .gamma_set = vop_crtc_gamma_set,
+ .set_config = drm_atomic_helper_set_config,
+ .page_flip = drm_atomic_helper_page_flip,
+ .destroy = vop_crtc_destroy,
+ .reset = vop_crtc_reset,
+ .set_property = drm_atomic_helper_crtc_set_property,
+ .atomic_get_property = vop_crtc_atomic_get_property,
+ .atomic_set_property = vop_crtc_atomic_set_property,
+ .atomic_duplicate_state = vop_crtc_duplicate_state,
+ .atomic_destroy_state = vop_crtc_destroy_state,
+};
+
+static void vop_fb_unref_worker(struct drm_flip_work *work, void *val)
{
- return !list_empty(&vop_win->pending);
+ struct vop *vop = container_of(work, struct vop, fb_unref_work);
+ struct drm_framebuffer *fb = val;
+
+ drm_crtc_vblank_put(&vop->crtc);
+ drm_framebuffer_unreference(fb);
}
-static irqreturn_t vop_isr_thread(int irq, void *data)
+static void vop_handle_vblank(struct vop *vop)
{
- struct vop *vop = data;
- const struct vop_data *vop_data = vop->data;
- unsigned int i;
-
- mutex_lock(&vop->vsync_mutex);
+ struct drm_device *drm = vop->drm_dev;
+ struct drm_crtc *crtc = &vop->crtc;
+ unsigned long flags;
- if (!vop->vsync_work_pending)
- goto done;
+ if (!vop_is_cfg_done_complete(vop))
+ return;
- vop->vsync_work_pending = false;
+ if (vop->event) {
+ spin_lock_irqsave(&drm->event_lock, flags);
- for (i = 0; i < vop_data->win_size; i++) {
- struct vop_win *vop_win = &vop->win[i];
+ drm_crtc_send_vblank_event(crtc, vop->event);
+ drm_crtc_vblank_put(crtc);
+ vop->event = NULL;
- vop_win_update_state(vop_win);
- if (vop_win_has_pending_state(vop_win))
- vop->vsync_work_pending = true;
+ spin_unlock_irqrestore(&drm->event_lock, flags);
}
-done:
- mutex_unlock(&vop->vsync_mutex);
-
- return IRQ_HANDLED;
+ if (test_and_clear_bit(VOP_PENDING_FB_UNREF, &vop->pending))
+ drm_flip_work_commit(&vop->fb_unref_work, system_unbound_wq);
}
static irqreturn_t vop_isr(int irq, void *data)
{
struct vop *vop = data;
- uint32_t intr0_reg, active_irqs;
+ struct drm_crtc *crtc = &vop->crtc;
+ uint32_t active_irqs;
unsigned long flags;
int ret = IRQ_NONE;
/*
- * INTR_CTRL0 register has interrupt status, enable and clear bits, we
+ * interrupt register has interrupt status, enable and clear bits, we
* must hold irq_lock to avoid a race with enable/disable_vblank().
*/
spin_lock_irqsave(&vop->irq_lock, flags);
- intr0_reg = vop_readl(vop, INTR_CTRL0);
- active_irqs = intr0_reg & INTR_MASK;
+
+ active_irqs = VOP_INTR_GET_TYPE(vop, status, INTR_MASK);
/* Clear all active interrupt sources */
if (active_irqs)
- vop_writel(vop, INTR_CTRL0,
- intr0_reg | (active_irqs << INTR_CLR_SHIFT));
+ VOP_INTR_SET_TYPE(vop, clear, active_irqs, 1);
+
spin_unlock_irqrestore(&vop->irq_lock, flags);
/* This is expected for vop iommu irqs, since the irq is shared */
ret = IRQ_HANDLED;
}
+ if (active_irqs & LINE_FLAG_INTR) {
+ complete(&vop->line_flag_completion);
+ active_irqs &= ~LINE_FLAG_INTR;
+ ret = IRQ_HANDLED;
+ }
+
if (active_irqs & FS_INTR) {
- drm_handle_vblank(vop->drm_dev, vop->pipe);
+ drm_crtc_handle_vblank(crtc);
+ vop_handle_vblank(vop);
active_irqs &= ~FS_INTR;
- ret = (vop->vsync_work_pending) ? IRQ_WAKE_THREAD : IRQ_HANDLED;
+ ret = IRQ_HANDLED;
}
+#define ERROR_HANDLER(x) \
+ do { \
+ if (active_irqs & x##_INTR) {\
+ DRM_DEV_ERROR_RATELIMITED(vop->dev, #x " irq err\n"); \
+ active_irqs &= ~x##_INTR; \
+ ret = IRQ_HANDLED; \
+ } \
+ } while (0)
+
+ ERROR_HANDLER(BUS_ERROR);
+ ERROR_HANDLER(WIN0_EMPTY);
+ ERROR_HANDLER(WIN1_EMPTY);
+ ERROR_HANDLER(WIN2_EMPTY);
+ ERROR_HANDLER(WIN3_EMPTY);
+ ERROR_HANDLER(HWC_EMPTY);
+ ERROR_HANDLER(POST_BUF_EMPTY);
+
/* Unhandled irqs are spurious. */
if (active_irqs)
DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
return ret;
}
+static int vop_plane_init(struct vop *vop, struct vop_win *win,
+ unsigned long possible_crtcs)
+{
+ struct rockchip_drm_private *private = vop->drm_dev->dev_private;
+ struct drm_plane *share = NULL;
+ unsigned int rotations = 0;
+ struct drm_property *prop;
+ uint64_t feature = 0;
+ int ret;
+
+ if (win->parent)
+ share = &win->parent->base;
+
+ ret = drm_share_plane_init(vop->drm_dev, &win->base, share,
+ possible_crtcs, &vop_plane_funcs,
+ win->data_formats, win->nformats, win->type);
+ if (ret) {
+ DRM_ERROR("failed to initialize plane\n");
+ return ret;
+ }
+ drm_plane_helper_add(&win->base, &plane_helper_funcs);
+ drm_object_attach_property(&win->base.base,
+ vop->plane_zpos_prop, win->win_id);
+
+ if (VOP_WIN_SUPPORT(vop, win, xmirror))
+ rotations |= BIT(DRM_REFLECT_X);
+
+ if (VOP_WIN_SUPPORT(vop, win, ymirror)) {
+ rotations |= BIT(DRM_REFLECT_Y);
+
+ prop = drm_property_create_bool(vop->drm_dev,
+ DRM_MODE_PROP_ATOMIC,
+ "LOGO_YMIRROR");
+ if (!prop)
+ return -ENOMEM;
+ private->logo_ymirror_prop = prop;
+ }
+
+ if (rotations) {
+ rotations |= BIT(DRM_ROTATE_0);
+ prop = drm_mode_create_rotation_property(vop->drm_dev,
+ rotations);
+ if (!prop) {
+ DRM_ERROR("failed to create zpos property\n");
+ return -EINVAL;
+ }
+ drm_object_attach_property(&win->base.base, prop,
+ BIT(DRM_ROTATE_0));
+ win->rotation_prop = prop;
+ }
+ if (win->phy->scl)
+ feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE);
+ if (VOP_WIN_SUPPORT(vop, win, src_alpha_ctl) ||
+ VOP_WIN_SUPPORT(vop, win, alpha_en))
+ feature |= BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA);
+
+ drm_object_attach_property(&win->base.base, vop->plane_feature_prop,
+ feature);
+
+ return 0;
+}
+
static int vop_create_crtc(struct vop *vop)
{
- const struct vop_data *vop_data = vop->data;
struct device *dev = vop->dev;
+ const struct vop_data *vop_data = vop->data;
struct drm_device *drm_dev = vop->drm_dev;
- struct drm_plane *primary = NULL, *cursor = NULL, *plane;
+ struct rockchip_drm_private *private = drm_dev->dev_private;
+ struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
struct drm_crtc *crtc = &vop->crtc;
struct device_node *port;
+ uint64_t feature = 0;
int ret;
int i;
* to pass them to drm_crtc_init_with_planes, which sets the
* "possible_crtcs" to the newly initialized crtc.
*/
- for (i = 0; i < vop_data->win_size; i++) {
- struct vop_win *vop_win = &vop->win[i];
- const struct vop_win_data *win_data = vop_win->data;
+ for (i = 0; i < vop->num_wins; i++) {
+ struct vop_win *win = &vop->win[i];
- if (win_data->type != DRM_PLANE_TYPE_PRIMARY &&
- win_data->type != DRM_PLANE_TYPE_CURSOR)
+ if (win->type != DRM_PLANE_TYPE_PRIMARY &&
+ win->type != DRM_PLANE_TYPE_CURSOR)
continue;
- ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
- 0, &vop_plane_funcs,
- win_data->phy->data_formats,
- win_data->phy->nformats,
- win_data->type);
- if (ret) {
- DRM_ERROR("failed to initialize plane\n");
+ ret = vop_plane_init(vop, win, 0);
+ if (ret)
goto err_cleanup_planes;
- }
- plane = &vop_win->base;
+ plane = &win->base;
if (plane->type == DRM_PLANE_TYPE_PRIMARY)
primary = plane;
else if (plane->type == DRM_PLANE_TYPE_CURSOR)
cursor = plane;
+
}
ret = drm_crtc_init_with_planes(drm_dev, crtc, primary, cursor,
- &vop_crtc_funcs);
+ &vop_crtc_funcs, NULL);
if (ret)
- return ret;
+ goto err_cleanup_planes;
drm_crtc_helper_add(crtc, &vop_crtc_helper_funcs);
* Create drm_planes for overlay windows with possible_crtcs restricted
* to the newly created crtc.
*/
- for (i = 0; i < vop_data->win_size; i++) {
- struct vop_win *vop_win = &vop->win[i];
- const struct vop_win_data *win_data = vop_win->data;
+ for (i = 0; i < vop->num_wins; i++) {
+ struct vop_win *win = &vop->win[i];
unsigned long possible_crtcs = 1 << drm_crtc_index(crtc);
- if (win_data->type != DRM_PLANE_TYPE_OVERLAY)
+ if (win->type != DRM_PLANE_TYPE_OVERLAY)
continue;
- ret = drm_universal_plane_init(vop->drm_dev, &vop_win->base,
- possible_crtcs,
- &vop_plane_funcs,
- win_data->phy->data_formats,
- win_data->phy->nformats,
- win_data->type);
- if (ret) {
- DRM_ERROR("failed to initialize overlay plane\n");
+ ret = vop_plane_init(vop, win, possible_crtcs);
+ if (ret)
goto err_cleanup_crtc;
- }
}
port = of_get_child_by_name(dev->of_node, "port");
if (!port) {
DRM_ERROR("no port node found in %s\n",
dev->of_node->full_name);
+ ret = -ENOENT;
goto err_cleanup_crtc;
}
+ drm_flip_work_init(&vop->fb_unref_work, "fb_unref",
+ vop_fb_unref_worker);
+
init_completion(&vop->dsp_hold_completion);
+ init_completion(&vop->line_flag_completion);
crtc->port = port;
- vop->pipe = drm_crtc_index(crtc);
- rockchip_register_crtc_funcs(drm_dev, &private_crtc_funcs, vop->pipe);
+ rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
+
+ ret = drm_mode_create_tv_properties(drm_dev, 0, NULL);
+ if (ret)
+ goto err_unregister_crtc_funcs;
+#define VOP_ATTACH_MODE_CONFIG_PROP(prop, v) \
+ drm_object_attach_property(&crtc->base, drm_dev->mode_config.prop, v)
+
+ VOP_ATTACH_MODE_CONFIG_PROP(tv_left_margin_property, 100);
+ VOP_ATTACH_MODE_CONFIG_PROP(tv_right_margin_property, 100);
+ VOP_ATTACH_MODE_CONFIG_PROP(tv_top_margin_property, 100);
+ VOP_ATTACH_MODE_CONFIG_PROP(tv_bottom_margin_property, 100);
+
+#undef VOP_ATTACH_MODE_CONFIG_PROP
+
+ drm_object_attach_property(&crtc->base, private->cabc_lut_property, 0);
+ drm_object_attach_property(&crtc->base, private->cabc_mode_property, 0);
+ drm_object_attach_property(&crtc->base, private->cabc_stage_up_property, 0);
+ drm_object_attach_property(&crtc->base, private->cabc_stage_down_property, 0);
+ drm_object_attach_property(&crtc->base, private->cabc_global_dn_property, 0);
+ drm_object_attach_property(&crtc->base, private->cabc_calc_pixel_num_property, 0);
+
+ if (vop_data->feature & VOP_FEATURE_AFBDC)
+ feature |= BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC);
+ drm_object_attach_property(&crtc->base, vop->feature_prop,
+ feature);
+ if (vop->lut_regs) {
+ u16 *r_base, *g_base, *b_base;
+ u32 lut_len = vop->lut_len;
+
+ drm_mode_crtc_set_gamma_size(crtc, lut_len);
+ vop->lut = devm_kmalloc_array(dev, lut_len, sizeof(*vop->lut),
+ GFP_KERNEL);
+ if (!vop->lut)
+ return -ENOMEM;
+
+ r_base = crtc->gamma_store;
+ g_base = r_base + crtc->gamma_size;
+ b_base = g_base + crtc->gamma_size;
+
+ for (i = 0; i < lut_len; i++) {
+ vop->lut[i] = i * lut_len * lut_len | i * lut_len | i;
+ rockchip_vop_crtc_fb_gamma_get(crtc, &r_base[i],
+ &g_base[i], &b_base[i],
+ i);
+ }
+ }
return 0;
+err_unregister_crtc_funcs:
+ rockchip_unregister_crtc_funcs(crtc);
err_cleanup_crtc:
drm_crtc_cleanup(crtc);
err_cleanup_planes:
- list_for_each_entry(plane, &drm_dev->mode_config.plane_list, head)
+ list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
+ head)
drm_plane_cleanup(plane);
return ret;
}
static void vop_destroy_crtc(struct vop *vop)
{
struct drm_crtc *crtc = &vop->crtc;
+ struct drm_device *drm_dev = vop->drm_dev;
+ struct drm_plane *plane, *tmp;
- rockchip_unregister_crtc_funcs(vop->drm_dev, vop->pipe);
+ rockchip_unregister_crtc_funcs(crtc);
of_node_put(crtc->port);
+
+ /*
+ * We need to cleanup the planes now. Why?
+ *
+ * The planes are "&vop->win[i].base". That means the memory is
+ * all part of the big "struct vop" chunk of memory. That memory
+ * was devm allocated and associated with this component. We need to
+ * free it ourselves before vop_unbind() finishes.
+ */
+ list_for_each_entry_safe(plane, tmp, &drm_dev->mode_config.plane_list,
+ head)
+ vop_plane_destroy(plane);
+
+ /*
+ * Destroy CRTC after vop_plane_destroy() since vop_disable_plane()
+ * references the CRTC.
+ */
drm_crtc_cleanup(crtc);
+ drm_flip_work_cleanup(&vop->fb_unref_work);
}
-static int vop_initial(struct vop *vop)
+/*
+ * Initialize the vop->win array elements.
+ */
+static int vop_win_init(struct vop *vop)
{
const struct vop_data *vop_data = vop->data;
- const struct vop_reg_data *init_table = vop_data->init_table;
- struct reset_control *ahb_rst;
- int i, ret;
+ unsigned int i, j;
+ unsigned int num_wins = 0;
+ struct drm_property *prop;
+ static const struct drm_prop_enum_list props[] = {
+ { ROCKCHIP_DRM_PLANE_FEATURE_SCALE, "scale" },
+ { ROCKCHIP_DRM_PLANE_FEATURE_ALPHA, "alpha" },
+ };
+ static const struct drm_prop_enum_list crtc_props[] = {
+ { ROCKCHIP_DRM_CRTC_FEATURE_AFBDC, "afbdc" },
+ };
- vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
- if (IS_ERR(vop->hclk)) {
- dev_err(vop->dev, "failed to get hclk source\n");
- return PTR_ERR(vop->hclk);
+ for (i = 0; i < vop_data->win_size; i++) {
+ struct vop_win *vop_win = &vop->win[num_wins];
+ const struct vop_win_data *win_data = &vop_data->win[i];
+
+ if (!win_data->phy)
+ continue;
+
+ vop_win->phy = win_data->phy;
+ vop_win->csc = win_data->csc;
+ vop_win->offset = win_data->base;
+ vop_win->type = win_data->type;
+ vop_win->data_formats = win_data->phy->data_formats;
+ vop_win->nformats = win_data->phy->nformats;
+ vop_win->vop = vop;
+ vop_win->win_id = i;
+ vop_win->area_id = 0;
+ num_wins++;
+
+ for (j = 0; j < win_data->area_size; j++) {
+ struct vop_win *vop_area = &vop->win[num_wins];
+ const struct vop_win_phy *area = win_data->area[j];
+
+ vop_area->parent = vop_win;
+ vop_area->offset = vop_win->offset;
+ vop_area->phy = area;
+ vop_area->type = DRM_PLANE_TYPE_OVERLAY;
+ vop_area->data_formats = vop_win->data_formats;
+ vop_area->nformats = vop_win->nformats;
+ vop_area->vop = vop;
+ vop_area->win_id = i;
+ vop_area->area_id = j;
+ num_wins++;
+ }
}
- vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
- if (IS_ERR(vop->aclk)) {
- dev_err(vop->dev, "failed to get aclk source\n");
- return PTR_ERR(vop->aclk);
+
+ vop->num_wins = num_wins;
+
+ prop = drm_property_create_range(vop->drm_dev, DRM_MODE_PROP_ATOMIC,
+ "ZPOS", 0, vop->data->win_size);
+ if (!prop) {
+ DRM_ERROR("failed to create zpos property\n");
+ return -EINVAL;
}
- vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
- if (IS_ERR(vop->dclk)) {
- dev_err(vop->dev, "failed to get dclk source\n");
- return PTR_ERR(vop->dclk);
+ vop->plane_zpos_prop = prop;
+
+ vop->plane_feature_prop = drm_property_create_bitmask(vop->drm_dev,
+ DRM_MODE_PROP_IMMUTABLE, "FEATURE",
+ props, ARRAY_SIZE(props),
+ BIT(ROCKCHIP_DRM_PLANE_FEATURE_SCALE) |
+ BIT(ROCKCHIP_DRM_PLANE_FEATURE_ALPHA));
+ if (!vop->plane_feature_prop) {
+ DRM_ERROR("failed to create feature property\n");
+ return -EINVAL;
}
- ret = clk_prepare(vop->dclk);
- if (ret < 0) {
- dev_err(vop->dev, "failed to prepare dclk\n");
- return ret;
+ vop->feature_prop = drm_property_create_bitmask(vop->drm_dev,
+ DRM_MODE_PROP_IMMUTABLE, "FEATURE",
+ crtc_props, ARRAY_SIZE(crtc_props),
+ BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC));
+ if (!vop->feature_prop) {
+ DRM_ERROR("failed to create vop feature property\n");
+ return -EINVAL;
}
- /* Enable both the hclk and aclk to setup the vop */
- ret = clk_prepare_enable(vop->hclk);
- if (ret < 0) {
- dev_err(vop->dev, "failed to prepare/enable hclk\n");
- goto err_unprepare_dclk;
- }
+ return 0;
+}
- ret = clk_prepare_enable(vop->aclk);
- if (ret < 0) {
- dev_err(vop->dev, "failed to prepare/enable aclk\n");
- goto err_disable_hclk;
- }
+/**
+ * rockchip_drm_wait_line_flag - acqiure the give line flag event
+ * @crtc: CRTC to enable line flag
+ * @line_num: interested line number
+ * @mstimeout: millisecond for timeout
+ *
+ * Driver would hold here until the interested line flag interrupt have
+ * happened or timeout to wait.
+ *
+ * Returns:
+ * Zero on success, negative errno on failure.
+ */
+int rockchip_drm_wait_line_flag(struct drm_crtc *crtc, unsigned int line_num,
+ unsigned int mstimeout)
+{
+ struct vop *vop = to_vop(crtc);
+ unsigned long jiffies_left;
+ int ret = 0;
- /*
- * do hclk_reset, reset all vop registers.
- */
- ahb_rst = devm_reset_control_get(vop->dev, "ahb");
- if (IS_ERR(ahb_rst)) {
- dev_err(vop->dev, "failed to get ahb reset\n");
- ret = PTR_ERR(ahb_rst);
- goto err_disable_aclk;
+ if (!crtc || !vop->is_enabled)
+ return -ENODEV;
+
+ mutex_lock(&vop->vop_lock);
+
+ if (line_num > crtc->mode.vtotal || mstimeout <= 0) {
+ ret = -EINVAL;
+ goto out;
}
- reset_control_assert(ahb_rst);
- usleep_range(10, 20);
- reset_control_deassert(ahb_rst);
- memcpy(vop->regsbak, vop->regs, vop->len);
+ if (vop_line_flag_irq_is_enabled(vop)) {
+ ret = -EBUSY;
+ goto out;
+ }
- for (i = 0; i < vop_data->table_size; i++)
- vop_writel(vop, init_table[i].offset, init_table[i].value);
+ reinit_completion(&vop->line_flag_completion);
+ vop_line_flag_irq_enable(vop, line_num);
- for (i = 0; i < vop_data->win_size; i++) {
- const struct vop_win_data *win = &vop_data->win[i];
+ jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
+ msecs_to_jiffies(mstimeout));
+ vop_line_flag_irq_disable(vop);
- VOP_WIN_SET(vop, win, enable, 0);
+ if (jiffies_left == 0) {
+ dev_err(vop->dev, "Timeout waiting for IRQ\n");
+ ret = -ETIMEDOUT;
+ goto out;
}
- vop_cfg_done(vop);
+out:
+ mutex_unlock(&vop->vop_lock);
- /*
- * do dclk_reset, let all config take affect.
- */
- vop->dclk_rst = devm_reset_control_get(vop->dev, "dclk");
- if (IS_ERR(vop->dclk_rst)) {
- dev_err(vop->dev, "failed to get dclk reset\n");
- ret = PTR_ERR(vop->dclk_rst);
- goto err_disable_aclk;
- }
- reset_control_assert(vop->dclk_rst);
- usleep_range(10, 20);
- reset_control_deassert(vop->dclk_rst);
+ return ret;
+}
+EXPORT_SYMBOL(rockchip_drm_wait_line_flag);
- clk_disable(vop->hclk);
- clk_disable(vop->aclk);
+static int dmc_notifier_call(struct notifier_block *nb, unsigned long event,
+ void *data)
+{
+ if (event == DEVFREQ_PRECHANGE)
+ mutex_lock(&dmc_vop->vop_lock);
+ else if (event == DEVFREQ_POSTCHANGE)
+ mutex_unlock(&dmc_vop->vop_lock);
- vop->is_enabled = false;
+ return NOTIFY_OK;
+}
- return 0;
+int rockchip_drm_register_notifier_to_dmc(struct devfreq *devfreq)
+{
+ if (!dmc_vop)
+ return -ENOMEM;
-err_disable_aclk:
- clk_disable_unprepare(vop->aclk);
-err_disable_hclk:
- clk_disable_unprepare(vop->hclk);
-err_unprepare_dclk:
- clk_unprepare(vop->dclk);
- return ret;
+ dmc_vop->devfreq = devfreq;
+ dmc_vop->dmc_nb.notifier_call = dmc_notifier_call;
+ devfreq_register_notifier(dmc_vop->devfreq, &dmc_vop->dmc_nb,
+ DEVFREQ_TRANSITION_NOTIFIER);
+ return 0;
}
+EXPORT_SYMBOL(rockchip_drm_register_notifier_to_dmc);
-/*
- * Initialize the vop->win array elements.
- */
-static void vop_win_init(struct vop *vop)
+static void vop_backlight_config_done(struct device *dev, bool async)
{
- const struct vop_data *vop_data = vop->data;
- unsigned int i;
+ struct vop *vop = dev_get_drvdata(dev);
- for (i = 0; i < vop_data->win_size; i++) {
- struct vop_win *vop_win = &vop->win[i];
- const struct vop_win_data *win_data = &vop_data->win[i];
+ if (vop && vop->is_enabled) {
+ int dle;
- vop_win->data = win_data;
- vop_win->vop = vop;
- INIT_LIST_HEAD(&vop_win->pending);
+ vop_cfg_done(vop);
+ if (!async) {
+ #define CTRL_GET(name) VOP_CTRL_GET(vop, name)
+ readx_poll_timeout(CTRL_GET, cfg_done,
+ dle, !dle, 5, 33333);
+ #undef CTRL_GET
+ }
}
}
+static const struct rockchip_sub_backlight_ops rockchip_sub_backlight_ops = {
+ .config_done = vop_backlight_config_done,
+};
+
static int vop_bind(struct device *dev, struct device *master, void *data)
{
struct platform_device *pdev = to_platform_device(dev);
- const struct of_device_id *of_id;
const struct vop_data *vop_data;
struct drm_device *drm_dev = data;
struct vop *vop;
struct resource *res;
size_t alloc_size;
- int ret, irq;
+ int ret, irq, i;
+ int num_wins = 0;
- of_id = of_match_device(vop_driver_dt_match, dev);
- vop_data = of_id->data;
+ vop_data = of_device_get_match_data(dev);
if (!vop_data)
return -ENODEV;
+ for (i = 0; i < vop_data->win_size; i++) {
+ const struct vop_win_data *win_data = &vop_data->win[i];
+
+ num_wins += win_data->area_size + 1;
+ }
+
/* Allocate vop struct and its vop_win array */
- alloc_size = sizeof(*vop) + sizeof(*vop->win) * vop_data->win_size;
+ alloc_size = sizeof(*vop) + sizeof(*vop->win) * num_wins;
vop = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
if (!vop)
return -ENOMEM;
vop->dev = dev;
vop->data = vop_data;
vop->drm_dev = drm_dev;
+ vop->num_wins = num_wins;
dev_set_drvdata(dev, vop);
- vop_win_init(vop);
+ ret = vop_win_init(vop);
+ if (ret)
+ return ret;
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- vop->len = resource_size(res);
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
+ if (!res) {
+ dev_warn(vop->dev, "failed to get vop register byname\n");
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ }
vop->regs = devm_ioremap_resource(dev, res);
if (IS_ERR(vop->regs))
return PTR_ERR(vop->regs);
+ vop->len = resource_size(res);
vop->regsbak = devm_kzalloc(dev, vop->len, GFP_KERNEL);
if (!vop->regsbak)
return -ENOMEM;
- ret = vop_initial(vop);
- if (ret < 0) {
- dev_err(&pdev->dev, "cannot initial vop dev - err %d\n", ret);
- return ret;
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gamma_lut");
+ vop->lut_regs = devm_ioremap_resource(dev, res);
+ if (IS_ERR(vop->lut_regs)) {
+ dev_warn(vop->dev, "failed to get vop lut registers\n");
+ vop->lut_regs = NULL;
+ }
+ if (vop->lut_regs) {
+ vop->lut_len = resource_size(res) / sizeof(*vop->lut);
+ if (vop->lut_len != 256 && vop->lut_len != 1024) {
+ dev_err(vop->dev, "unsupport lut sizes %d\n",
+ vop->lut_len);
+ return -EINVAL;
+ }
+ }
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cabc_lut");
+ vop->cabc_lut_regs = devm_ioremap_resource(dev, res);
+ if (IS_ERR(vop->cabc_lut_regs)) {
+ dev_warn(vop->dev, "failed to get vop cabc lut registers\n");
+ vop->cabc_lut_regs = NULL;
+ }
+
+ if (vop->cabc_lut_regs) {
+ vop->cabc_lut_len = resource_size(res) >> 2;
+ if (vop->cabc_lut_len != 128) {
+ dev_err(vop->dev, "unsupport cabc lut sizes %d\n",
+ vop->cabc_lut_len);
+ return -EINVAL;
+ }
+ }
+
+ vop->hclk = devm_clk_get(vop->dev, "hclk_vop");
+ if (IS_ERR(vop->hclk)) {
+ dev_err(vop->dev, "failed to get hclk source\n");
+ return PTR_ERR(vop->hclk);
+ }
+ vop->aclk = devm_clk_get(vop->dev, "aclk_vop");
+ if (IS_ERR(vop->aclk)) {
+ dev_err(vop->dev, "failed to get aclk source\n");
+ return PTR_ERR(vop->aclk);
+ }
+ vop->dclk = devm_clk_get(vop->dev, "dclk_vop");
+ if (IS_ERR(vop->dclk)) {
+ dev_err(vop->dev, "failed to get dclk source\n");
+ return PTR_ERR(vop->dclk);
+ }
+
+ vop->dclk_source = devm_clk_get(vop->dev, "dclk_source");
+ if (PTR_ERR(vop->dclk_source) == -ENOENT) {
+ vop->dclk_source = NULL;
+ } else if (PTR_ERR(vop->dclk_source) == -EPROBE_DEFER) {
+ return -EPROBE_DEFER;
+ } else if (IS_ERR(vop->dclk_source)) {
+ dev_err(vop->dev, "failed to get dclk source parent\n");
+ return PTR_ERR(vop->dclk_source);
}
irq = platform_get_irq(pdev, 0);
spin_lock_init(&vop->reg_lock);
spin_lock_init(&vop->irq_lock);
+ mutex_init(&vop->vop_lock);
mutex_init(&vop->vsync_mutex);
- ret = devm_request_threaded_irq(dev, vop->irq, vop_isr, vop_isr_thread,
- IRQF_SHARED, dev_name(dev), vop);
+ ret = devm_request_irq(dev, vop->irq, vop_isr,
+ IRQF_SHARED, dev_name(dev), vop);
if (ret)
return ret;
return ret;
pm_runtime_enable(&pdev->dev);
+
+ of_rockchip_drm_sub_backlight_register(dev, &vop->crtc,
+ &rockchip_sub_backlight_ops);
+
+ dmc_vop = vop;
+
return 0;
}
vop_destroy_crtc(vop);
}
-static const struct component_ops vop_component_ops = {
+const struct component_ops vop_component_ops = {
.bind = vop_bind,
.unbind = vop_unbind,
};
-
-static int vop_probe(struct platform_device *pdev)
-{
- struct device *dev = &pdev->dev;
-
- if (!dev->of_node) {
- dev_err(dev, "can't find vop devices\n");
- return -ENODEV;
- }
-
- return component_add(dev, &vop_component_ops);
-}
-
-static int vop_remove(struct platform_device *pdev)
-{
- component_del(&pdev->dev, &vop_component_ops);
-
- return 0;
-}
-
-struct platform_driver vop_platform_driver = {
- .probe = vop_probe,
- .remove = vop_remove,
- .driver = {
- .name = "rockchip-vop",
- .owner = THIS_MODULE,
- .of_match_table = of_match_ptr(vop_driver_dt_match),
- },
-};
-
-module_platform_driver(vop_platform_driver);
-
-MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>");
-MODULE_DESCRIPTION("ROCKCHIP VOP Driver");
-MODULE_LICENSE("GPL v2");
+EXPORT_SYMBOL_GPL(vop_component_ops);
projects / firefly-linux-kernel-4.4.55.git / blobdiff