#include <drm/drm_crtc_helper.h>
#include <drm/drm_plane_helper.h>
+#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#define VOP_WIN_SET(x, win, name, v) \
REG_SET(x, name, win->offset, VOP_WIN_NAME(win, name), v, true)
#define VOP_WIN_SET_EXT(x, win, ext, name, v) \
- REG_SET(x, name, win->offset, win->ext->name, v, true)
+ REG_SET(x, name, 0, win->ext->name, v, true)
#define VOP_SCL_SET(x, win, name, v) \
REG_SET(x, name, win->offset, win->phy->scl->name, v, true)
#define VOP_SCL_SET_EXT(x, win, name, v) \
#define VOP_INTR_GET(vop, name) \
vop_read_reg(vop, 0, &vop->data->ctrl->name)
-#define VOP_INTR_SET(vop, name, mask, v) \
+#define VOP_INTR_SET(vop, name, v) \
+ REG_SET(vop, name, 0, vop->data->intr->name, \
+ v, false)
+#define VOP_INTR_SET_MASK(vop, name, mask, v) \
REG_SET_MASK(vop, name, 0, vop->data->intr->name, \
mask, v, false)
mask |= 1 << i; \
} \
} \
- VOP_INTR_SET(vop, name, mask, reg); \
+ VOP_INTR_SET_MASK(vop, name, mask, reg); \
} while (0)
#define VOP_INTR_GET_TYPE(vop, name, type) \
vop_get_intr_type(vop, &vop->data->intr->name, type)
/* mutex vsync_ work */
struct mutex vsync_mutex;
bool vsync_work_pending;
+ bool loader_protect;
struct completion dsp_hold_completion;
struct completion wait_update_complete;
struct drm_pending_vblank_event *event;
+ struct completion line_flag_completion;
+
const struct vop_data *data;
int num_wins;
return VOP_CTRL_GET(vop, cfg_done) ? false : true;
}
+static bool vop_fs_irq_is_active(struct vop *vop)
+{
+ return VOP_INTR_GET_TYPE(vop, status, FS_INTR);
+}
+
+static bool vop_line_flag_is_active(struct vop *vop)
+{
+ return VOP_INTR_GET_TYPE(vop, status, LINE_FLAG_INTR);
+}
+
static bool has_rb_swapped(uint32_t format)
{
switch (format) {
}
}
+static bool is_yuv_output(uint32_t bus_format)
+{
+ switch (bus_format) {
+ case MEDIA_BUS_FMT_YUV8_1X24:
+ case MEDIA_BUS_FMT_YUV10_1X30:
+ return true;
+ default:
+ return false;
+ }
+}
+
static bool is_yuv_support(uint32_t format)
{
switch (format) {
if (!win->phy->scl)
return;
- if (dst_w > 3840) {
- DRM_ERROR("Maximum destination width (3840) exceeded\n");
- return;
- }
-
if (!win->phy->scl->ext) {
VOP_SCL_SET(vop, win, scale_yrgb_x,
scl_cal_scale2(src_w, dst_w));
*y2r_table = csc_table->y2r_bt2020;
if (input_csc == CSC_BT2020)
*r2r_table = csc_table->r2r_bt2020_to_bt709;
- if (!is_input_yuv || y2r_table) {
+ if (!is_input_yuv || *y2r_table) {
if (output_csc == CSC_BT709)
*r2y_table = csc_table->r2y_bt709;
else
*r2y_table = csc_table->r2y_bt601;
}
}
-
} else {
if (!is_input_yuv)
return 0;
{
struct vop *vop = to_vop(crtc);
struct drm_atomic_state *state = crtc_state->state;
+ struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
const struct vop_csc_table *csc_table = vop->data->csc_table;
struct drm_plane_state *pstate;
struct drm_plane *plane;
- bool is_yuv;
+ bool is_input_yuv, is_output_yuv;
int ret;
if (!csc_table)
return 0;
+ is_output_yuv = is_yuv_output(s->bus_format);
+
drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
struct vop_plane_state *vop_plane_state;
if (!pstate->fb)
continue;
- is_yuv = is_yuv_support(pstate->fb->pixel_format);
+ is_input_yuv = is_yuv_support(pstate->fb->pixel_format);
/*
* TODO: force set input and output csc mode.
*/
- ret = vop_csc_setup(csc_table, is_yuv, false,
+ ret = vop_csc_setup(csc_table, is_input_yuv, is_output_yuv,
CSC_BT709, CSC_BT709,
&vop_plane_state->y2r_table,
&vop_plane_state->r2r_table,
spin_lock_irqsave(&vop->irq_lock, flags);
+ VOP_INTR_SET_TYPE(vop, clear, DSP_HOLD_VALID_INTR, 1);
VOP_INTR_SET_TYPE(vop, enable, DSP_HOLD_VALID_INTR, 1);
spin_unlock_irqrestore(&vop->irq_lock, flags);
spin_unlock_irqrestore(&vop->irq_lock, flags);
}
-static void vop_enable(struct drm_crtc *crtc)
+/*
+ * (1) each frame starts at the start of the Vsync pulse which is signaled by
+ * the "FRAME_SYNC" interrupt.
+ * (2) the active data region of each frame ends at dsp_vact_end
+ * (3) we should program this same number (dsp_vact_end) into dsp_line_frag_num,
+ * to get "LINE_FLAG" interrupt at the end of the active on screen data.
+ *
+ * VOP_INTR_CTRL0.dsp_line_frag_num = VOP_DSP_VACT_ST_END.dsp_vact_end
+ * Interrupts
+ * LINE_FLAG -------------------------------+
+ * FRAME_SYNC ----+ |
+ * | |
+ * v v
+ * | Vsync | Vbp | Vactive | Vfp |
+ * ^ ^ ^ ^
+ * | | | |
+ * | | | |
+ * dsp_vs_end ------------+ | | | VOP_DSP_VTOTAL_VS_END
+ * dsp_vact_start --------------+ | | VOP_DSP_VACT_ST_END
+ * dsp_vact_end ----------------------------+ | VOP_DSP_VACT_ST_END
+ * dsp_total -------------------------------------+ VOP_DSP_VTOTAL_VS_END
+ */
+static bool vop_line_flag_irq_is_enabled(struct vop *vop)
+{
+ uint32_t line_flag_irq;
+ unsigned long flags;
+
+ spin_lock_irqsave(&vop->irq_lock, flags);
+
+ line_flag_irq = VOP_INTR_GET_TYPE(vop, enable, LINE_FLAG_INTR);
+
+ spin_unlock_irqrestore(&vop->irq_lock, flags);
+
+ return !!line_flag_irq;
+}
+
+static void vop_line_flag_irq_enable(struct vop *vop, int line_num)
+{
+ unsigned long flags;
+
+ if (WARN_ON(!vop->is_enabled))
+ return;
+
+ spin_lock_irqsave(&vop->irq_lock, flags);
+
+ VOP_INTR_SET(vop, line_flag_num[0], line_num);
+ VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
+ VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
+
+ spin_unlock_irqrestore(&vop->irq_lock, flags);
+}
+
+static void vop_line_flag_irq_disable(struct vop *vop)
+{
+ unsigned long flags;
+
+ if (WARN_ON(!vop->is_enabled))
+ return;
+
+ spin_lock_irqsave(&vop->irq_lock, flags);
+
+ VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
+
+ spin_unlock_irqrestore(&vop->irq_lock, flags);
+}
+
+static void vop_power_enable(struct drm_crtc *crtc)
{
struct vop *vop = to_vop(crtc);
- int ret, i;
+ int ret;
ret = clk_prepare_enable(vop->hclk);
if (ret < 0) {
memcpy(vop->regsbak, vop->regs, vop->len);
- VOP_CTRL_SET(vop, global_regdone_en, 1);
- VOP_CTRL_SET(vop, dsp_blank, 0);
-
- for (i = 0; i < vop->num_wins; i++) {
- struct vop_win *win = &vop->win[i];
-
- VOP_WIN_SET(vop, win, gate, 1);
- }
vop->is_enabled = true;
- spin_lock(&vop->reg_lock);
-
- VOP_CTRL_SET(vop, standby, 0);
-
- spin_unlock(&vop->reg_lock);
-
- enable_irq(vop->irq);
-
- drm_crtc_vblank_on(crtc);
-
return;
err_disable_dclk:
clk_disable_unprepare(vop->hclk);
}
-static void vop_crtc_disable(struct drm_crtc *crtc)
+static void vop_initial(struct drm_crtc *crtc)
{
struct vop *vop = to_vop(crtc);
int i;
+ vop_power_enable(crtc);
+
+ VOP_CTRL_SET(vop, global_regdone_en, 1);
+ VOP_CTRL_SET(vop, dsp_blank, 0);
+
/*
- * We need to make sure that all windows are disabled before we
- * disable that crtc. Otherwise we might try to scan from a destroyed
+ * We need to make sure that all windows are disabled before resume
+ * the crtc. Otherwise we might try to scan from a destroyed
* buffer later.
*/
for (i = 0; i < vop->num_wins; i++) {
struct vop_win *win = &vop->win[i];
+ int channel = i * 2 + 1;
- spin_lock(&vop->reg_lock);
+ VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
if (win->phy->scl && win->phy->scl->ext) {
VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
}
VOP_WIN_SET(vop, win, enable, 0);
- spin_unlock(&vop->reg_lock);
+ VOP_WIN_SET(vop, win, gate, 1);
}
VOP_CTRL_SET(vop, afbdc_en, 0);
- vop_cfg_done(vop);
+}
+
+static void vop_crtc_disable(struct drm_crtc *crtc)
+{
+ struct vop *vop = to_vop(crtc);
drm_crtc_vblank_off(crtc);
spin_unlock(&vop->reg_lock);
- wait_for_completion(&vop->dsp_hold_completion);
+ WARN_ON(!wait_for_completion_timeout(&vop->dsp_hold_completion,
+ msecs_to_jiffies(50)));
vop_dsp_hold_valid_irq_disable(vop);
struct vop_win *win = to_vop_win(plane);
struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
struct drm_crtc_state *crtc_state;
+ const struct vop_data *vop_data;
+ struct vop *vop;
bool visible;
int ret;
struct drm_rect *dest = &vop_plane_state->dest;
DRM_PLANE_HELPER_NO_SCALING;
unsigned long offset;
dma_addr_t dma_addr;
+ u16 vdisplay;
crtc = crtc ? crtc : plane->state->crtc;
/*
dest->x2 = state->crtc_x + state->crtc_w;
dest->y2 = state->crtc_y + state->crtc_h;
+ vdisplay = crtc_state->adjusted_mode.crtc_vdisplay;
+ if (crtc_state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
+ vdisplay *= 2;
+
clip.x1 = 0;
clip.y1 = 0;
- clip.x2 = crtc_state->mode.hdisplay;
- clip.y2 = crtc_state->mode.vdisplay;
+ clip.x2 = crtc_state->adjusted_mode.crtc_hdisplay;
+ clip.y2 = vdisplay;
ret = drm_plane_helper_check_update(plane, crtc, state->fb,
src, dest, &clip,
if (vop_plane_state->format < 0)
return vop_plane_state->format;
+ vop = to_vop(crtc);
+ vop_data = vop->data;
+
+ if (drm_rect_width(src) >> 16 > vop_data->max_input.width ||
+ drm_rect_height(src) >> 16 > vop_data->max_input.height) {
+ DRM_ERROR("Invalid source: %dx%d. max input: %dx%d\n",
+ drm_rect_width(src) >> 16,
+ drm_rect_height(src) >> 16,
+ vop_data->max_input.width,
+ vop_data->max_input.height);
+ return -EINVAL;
+ }
+
/*
* Src.x1 can be odd when do clip, but yuv plane start point
* need align with 2 pixel.
*/
- if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2))
+ if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2)) {
+ DRM_ERROR("Invalid Source: Yuv format Can't support odd xpos\n");
return -EINVAL;
+ }
offset = (src->x1 >> 16) * drm_format_plane_bpp(fb->pixel_format, 0) / 8;
if (state->rotation & BIT(DRM_REFLECT_Y))
struct drm_crtc *crtc = state->crtc;
struct vop_win *win = to_vop_win(plane);
struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
- struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
- struct vop *vop = to_vop(state->crtc);
+ struct rockchip_crtc_state *s;
+ struct vop *vop;
struct drm_framebuffer *fb = state->fb;
unsigned int actual_w, actual_h;
unsigned int dsp_stx, dsp_sty;
ymirror = !!(state->rotation & BIT(DRM_REFLECT_Y));
xmirror = !!(state->rotation & BIT(DRM_REFLECT_X));
+ vop = to_vop(state->crtc);
+ s = to_rockchip_crtc_state(crtc->state);
+
spin_lock(&vop->reg_lock);
VOP_WIN_SET(vop, win, xmirror, xmirror);
if (win->csc) {
vop_load_csc_table(vop, win->csc->y2r_offset, y2r_table);
vop_load_csc_table(vop, win->csc->r2r_offset, r2r_table);
- vop_load_csc_table(vop, win->csc->r2r_offset, r2y_table);
+ vop_load_csc_table(vop, win->csc->r2y_offset, r2y_table);
VOP_WIN_SET_EXT(vop, win, csc, y2r_en, !!y2r_table);
VOP_WIN_SET_EXT(vop, win, csc, r2r_en, !!r2r_table);
VOP_WIN_SET_EXT(vop, win, csc, r2y_en, !!r2y_table);
spin_lock_irqsave(&vop->irq_lock, flags);
+ VOP_INTR_SET_TYPE(vop, clear, FS_INTR, 1);
VOP_INTR_SET_TYPE(vop, enable, FS_INTR, 1);
spin_unlock_irqrestore(&vop->irq_lock, flags);
spin_unlock_irqrestore(&drm->event_lock, flags);
}
+static int vop_crtc_loader_protect(struct drm_crtc *crtc, bool on)
+{
+ struct vop *vop = to_vop(crtc);
+
+ if (on == vop->loader_protect)
+ return 0;
+
+ if (on) {
+ vop_power_enable(crtc);
+ enable_irq(vop->irq);
+ drm_crtc_vblank_on(crtc);
+ vop->loader_protect = true;
+ } else {
+ vop_crtc_disable(crtc);
+
+ vop->loader_protect = false;
+ }
+
+ return 0;
+}
+
+static int vop_plane_info_dump(struct seq_file *s, struct drm_plane *plane)
+{
+ struct vop_win *win = to_vop_win(plane);
+ struct drm_plane_state *state = plane->state;
+ struct vop_plane_state *pstate = to_vop_plane_state(state);
+ struct drm_rect *src, *dest;
+ struct drm_framebuffer *fb = state->fb;
+ int i;
+
+ seq_printf(s, " win%d-%d: %s\n", win->win_id, win->area_id,
+ pstate->enable ? "ACTIVE" : "DISABLED");
+ if (!fb)
+ return 0;
+
+ src = &pstate->src;
+ dest = &pstate->dest;
+
+ seq_printf(s, "\tformat: %s%s\n", drm_get_format_name(fb->pixel_format),
+ fb->modifier[0] == DRM_FORMAT_MOD_ARM_AFBC ? "[AFBC]" : "");
+ seq_printf(s, "\tzpos: %d\n", pstate->zpos);
+ seq_printf(s, "\tsrc: pos[%dx%d] rect[%dx%d]\n", src->x1 >> 16,
+ src->y1 >> 16, drm_rect_width(src) >> 16,
+ drm_rect_height(src) >> 16);
+ seq_printf(s, "\tdst: pos[%dx%d] rect[%dx%d]\n", dest->x1, dest->y1,
+ drm_rect_width(dest), drm_rect_height(dest));
+
+ for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
+ dma_addr_t fb_addr = rockchip_fb_get_dma_addr(fb, i);
+ seq_printf(s, "\tbuf[%d]: addr: %pad pitch: %d offset: %d\n",
+ i, &fb_addr, fb->pitches[i], fb->offsets[i]);
+ }
+
+ return 0;
+}
+
+static int vop_crtc_debugfs_dump(struct drm_crtc *crtc, struct seq_file *s)
+{
+ struct vop *vop = to_vop(crtc);
+ struct drm_crtc_state *crtc_state = crtc->state;
+ struct drm_display_mode *mode = &crtc->state->adjusted_mode;
+ struct rockchip_crtc_state *state = to_rockchip_crtc_state(crtc->state);
+ bool interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
+ struct drm_plane *plane;
+ int i;
+
+ seq_printf(s, "VOP [%s]: %s\n", dev_name(vop->dev),
+ crtc_state->active ? "ACTIVE" : "DISABLED");
+
+ if (!crtc_state->active)
+ return 0;
+
+ seq_printf(s, " Connector: %s\n",
+ drm_get_connector_name(state->output_type));
+ seq_printf(s, "\tbus_format[%x] output_mode[%x]\n",
+ state->bus_format, state->output_mode);
+ seq_printf(s, " Display mode: %dx%d%s%d\n",
+ mode->hdisplay, mode->vdisplay, interlaced ? "i" : "p",
+ drm_mode_vrefresh(mode));
+ seq_printf(s, "\tclk[%d] real_clk[%d] type[%x] flag[%x]\n",
+ mode->clock, mode->crtc_clock, mode->type, mode->flags);
+ seq_printf(s, "\tH: %d %d %d %d\n", mode->hdisplay, mode->hsync_start,
+ mode->hsync_end, mode->htotal);
+ seq_printf(s, "\tV: %d %d %d %d\n", mode->vdisplay, mode->vsync_start,
+ mode->vsync_end, mode->vtotal);
+
+ for (i = 0; i < vop->num_wins; i++) {
+ plane = &vop->win[i].base;
+ vop_plane_info_dump(s, plane);
+ }
+
+ return 0;
+}
+
+static enum drm_mode_status
+vop_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode,
+ int output_type)
+{
+ struct vop *vop = to_vop(crtc);
+ const struct vop_data *vop_data = vop->data;
+ int request_clock = mode->clock;
+ int clock;
+
+ if (mode->hdisplay > vop_data->max_output.width)
+ return MODE_BAD_HVALUE;
+ if (mode->vdisplay > vop_data->max_output.height)
+ return MODE_BAD_VVALUE;
+
+ if (mode->flags & DRM_MODE_FLAG_DBLCLK)
+ request_clock *= 2;
+ clock = clk_round_rate(vop->dclk, request_clock * 1000) / 1000;
+
+ /*
+ * Hdmi or DisplayPort request a Accurate clock.
+ */
+ if (output_type == DRM_MODE_CONNECTOR_HDMIA ||
+ output_type == DRM_MODE_CONNECTOR_DisplayPort)
+ if (clock != request_clock)
+ return MODE_CLOCK_RANGE;
+
+ return MODE_OK;
+}
+
static const struct rockchip_crtc_funcs private_crtc_funcs = {
+ .loader_protect = vop_crtc_loader_protect,
.enable_vblank = vop_crtc_enable_vblank,
.disable_vblank = vop_crtc_disable_vblank,
.wait_for_update = vop_crtc_wait_for_update,
.cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
+ .debugfs_dump = vop_crtc_debugfs_dump,
+ .mode_valid = vop_crtc_mode_valid,
};
static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
const struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode)
+ struct drm_display_mode *adj_mode)
{
struct vop *vop = to_vop(crtc);
+ const struct vop_data *vop_data = vop->data;
+
+ if (mode->hdisplay > vop_data->max_output.width ||
+ mode->vdisplay > vop_data->max_output.height)
+ return false;
+
+ drm_mode_set_crtcinfo(adj_mode,
+ CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE);
+
+ if (mode->flags & DRM_MODE_FLAG_DBLCLK)
+ adj_mode->crtc_clock *= 2;
- adjusted_mode->clock =
- clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
+ adj_mode->crtc_clock =
+ clk_round_rate(vop->dclk, adj_mode->crtc_clock * 1000) / 1000;
return true;
}
u16 vact_end = vact_st + vdisplay;
uint32_t val;
- vop_enable(crtc);
- /*
- * If dclk rate is zero, mean that scanout is stop,
- * we don't need wait any more.
- */
- if (clk_get_rate(vop->dclk)) {
- /*
- * Rk3288 vop timing register is immediately, when configure
- * display timing on display time, may cause tearing.
- *
- * Vop standby will take effect at end of current frame,
- * if dsp hold valid irq happen, it means standby complete.
- *
- * mode set:
- * standby and wait complete --> |----
- * | display time
- * |----
- * |---> dsp hold irq
- * configure display timing --> |
- * standby exit |
- * | new frame start.
- */
-
- reinit_completion(&vop->dsp_hold_completion);
- vop_dsp_hold_valid_irq_enable(vop);
-
- spin_lock(&vop->reg_lock);
-
- VOP_CTRL_SET(vop, standby, 1);
-
- spin_unlock(&vop->reg_lock);
-
- wait_for_completion(&vop->dsp_hold_completion);
+ vop_initial(crtc);
- vop_dsp_hold_valid_irq_disable(vop);
- }
-
- val = 0x8;
- val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1;
- val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : (1 << 1);
+ val = BIT(DCLK_INVERT);
+ val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ?
+ 0 : BIT(HSYNC_POSITIVE);
+ val |= (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) ?
+ 0 : BIT(VSYNC_POSITIVE);
VOP_CTRL_SET(vop, pin_pol, val);
switch (s->output_type) {
case DRM_MODE_CONNECTOR_LVDS:
VOP_CTRL_SET(vop, mipi_en, 1);
VOP_CTRL_SET(vop, mipi_pin_pol, val);
break;
+ case DRM_MODE_CONNECTOR_DisplayPort:
+ val &= ~BIT(DCLK_INVERT);
+ VOP_CTRL_SET(vop, dp_pin_pol, val);
+ VOP_CTRL_SET(vop, dp_en, 1);
+ break;
default:
DRM_ERROR("unsupport connector_type[%d]\n", s->output_type);
}
s->output_mode = ROCKCHIP_OUT_MODE_P888;
VOP_CTRL_SET(vop, out_mode, s->output_mode);
+ switch (s->bus_format) {
+ case MEDIA_BUS_FMT_RGB565_1X16:
+ val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB565);
+ break;
+ case MEDIA_BUS_FMT_RGB666_1X18:
+ case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
+ val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB666);
+ break;
+ case MEDIA_BUS_FMT_YUV8_1X24:
+ val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(1);
+ break;
+ case MEDIA_BUS_FMT_YUV10_1X30:
+ val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
+ break;
+ case MEDIA_BUS_FMT_RGB888_1X24:
+ default:
+ val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
+ break;
+ }
+
+ if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA)
+ val |= PRE_DITHER_DOWN_EN(0);
+ else
+ val |= PRE_DITHER_DOWN_EN(1);
+ val |= DITHER_DOWN_MODE_SEL(DITHER_DOWN_ALLEGRO);
+ VOP_CTRL_SET(vop, dither_down, val);
+ VOP_CTRL_SET(vop, dclk_ddr,
+ s->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0);
+ VOP_CTRL_SET(vop, overlay_mode, is_yuv_output(s->bus_format));
+ VOP_CTRL_SET(vop, dsp_out_yuv, is_yuv_output(s->bus_format));
+ VOP_CTRL_SET(vop, dsp_background,
+ is_yuv_output(s->bus_format) ? 0x20010200 : 0);
VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
val = hact_st << 16;
VOP_CTRL_SET(vop, hact_st_end, val);
VOP_CTRL_SET(vop, hpost_st_end, val);
- VOP_CTRL_SET(vop, vtotal_pw, (adjusted_mode->vtotal << 16) | vsync_len);
val = vact_st << 16;
val |= vact_end;
VOP_CTRL_SET(vop, vact_st_end, val);
VOP_CTRL_SET(vop, vs_st_end_f1, val);
VOP_CTRL_SET(vop, dsp_interlace, 1);
VOP_CTRL_SET(vop, p2i_en, 1);
+ vtotal += vtotal + 1;
} else {
VOP_CTRL_SET(vop, dsp_interlace, 0);
VOP_CTRL_SET(vop, p2i_en, 0);
}
+ VOP_CTRL_SET(vop, vtotal_pw, vtotal << 16 | vsync_len);
+
+ VOP_CTRL_SET(vop, core_dclk_div,
+ !!(adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK));
- clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
+ clk_set_rate(vop->dclk, adjusted_mode->crtc_clock * 1000);
+ vop_cfg_done(vop);
+ /*
+ * enable vop, all the register would take effect when vop exit standby
+ */
VOP_CTRL_SET(vop, standby, 0);
+
+ enable_irq(vop->irq);
+ drm_crtc_vblank_on(crtc);
}
static int vop_zpos_cmp(const void *a, const void *b)
return ret;
}
+static void vop_post_config(struct drm_crtc *crtc)
+{
+ struct vop *vop = to_vop(crtc);
+ struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
+ struct drm_display_mode *mode = &crtc->state->adjusted_mode;
+ u16 vtotal = mode->crtc_vtotal;
+ u16 hdisplay = mode->crtc_hdisplay;
+ u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start;
+ u16 vdisplay = mode->crtc_vdisplay;
+ u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start;
+ u16 hsize = hdisplay * (s->left_margin + s->right_margin) / 200;
+ u16 vsize = vdisplay * (s->top_margin + s->bottom_margin) / 200;
+ u16 hact_end, vact_end;
+ u32 val;
+
+ hact_st += hdisplay * (100 - s->left_margin) / 200;
+ hact_end = hact_st + hsize;
+ val = hact_st << 16;
+ val |= hact_end;
+ VOP_CTRL_SET(vop, hpost_st_end, val);
+ vact_st += vdisplay * (100 - s->top_margin) / 200;
+ vact_end = vact_st + vsize;
+ val = vact_st << 16;
+ val |= vact_end;
+ VOP_CTRL_SET(vop, vpost_st_end, val);
+ val = scl_cal_scale2(vdisplay, vsize) << 16;
+ val |= scl_cal_scale2(hdisplay, hsize);
+ VOP_CTRL_SET(vop, post_scl_factor, val);
+ VOP_CTRL_SET(vop, post_scl_ctrl, 0x3);
+ if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
+ u16 vact_st_f1 = vtotal + vact_st + 1;
+ u16 vact_end_f1 = vact_st_f1 + vsize;
+
+ val = vact_st_f1 << 16 | vact_end_f1;
+ VOP_CTRL_SET(vop, vpost_st_end_f1, val);
+ }
+}
+
static void vop_cfg_update(struct drm_crtc *crtc,
struct drm_crtc_state *old_crtc_state)
{
VOP_CTRL_SET(vop, afbdc_en, s->afbdc_en);
VOP_CTRL_SET(vop, dsp_layer_sel, s->dsp_layer_sel);
- vop_cfg_done(vop);
+ vop_post_config(crtc);
spin_unlock(&vop->reg_lock);
}
{
struct vop *vop = to_vop(crtc);
+ vop_cfg_update(crtc, old_crtc_state);
+
if (!vop->is_iommu_enabled && vop->is_iommu_needed) {
+ bool need_wait_vblank = !vop_is_allwin_disabled(vop);
int ret;
- if (!vop_is_allwin_disabled(vop)) {
- reinit_completion(&vop->dsp_hold_completion);
- vop_dsp_hold_valid_irq_enable(vop);
- vop_cfg_update(crtc, old_crtc_state);
- spin_lock(&vop->reg_lock);
+ if (need_wait_vblank) {
+ bool active;
- VOP_CTRL_SET(vop, standby, 1);
+ disable_irq(vop->irq);
+ drm_crtc_vblank_get(crtc);
+ VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 1);
- spin_unlock(&vop->reg_lock);
+ ret = readx_poll_timeout_atomic(vop_fs_irq_is_active,
+ vop, active, active,
+ 0, 50 * 1000);
+ if (ret)
+ dev_err(vop->dev, "wait fs irq timeout\n");
- wait_for_completion(&vop->dsp_hold_completion);
+ VOP_INTR_SET_TYPE(vop, clear, LINE_FLAG_INTR, 1);
+ vop_cfg_done(vop);
- vop_dsp_hold_valid_irq_disable(vop);
+ ret = readx_poll_timeout_atomic(vop_line_flag_is_active,
+ vop, active, active,
+ 0, 50 * 1000);
+ if (ret)
+ dev_err(vop->dev, "wait line flag timeout\n");
+
+ enable_irq(vop->irq);
}
ret = rockchip_drm_dma_attach_device(vop->drm_dev, vop->dev);
- if (ret) {
- dev_err(vop->dev, "failed to attach dma mapping, %d\n", ret);
+ if (ret)
+ dev_err(vop->dev, "failed to attach dma mapping, %d\n",
+ ret);
+
+ if (need_wait_vblank) {
+ VOP_INTR_SET_TYPE(vop, enable, LINE_FLAG_INTR, 0);
+ drm_crtc_vblank_put(crtc);
}
- VOP_CTRL_SET(vop, standby, 0);
+
vop->is_iommu_enabled = true;
}
- vop_cfg_update(crtc, old_crtc_state);
+ vop_cfg_done(vop);
}
static void vop_crtc_atomic_begin(struct drm_crtc *crtc,
static void vop_crtc_reset(struct drm_crtc *crtc)
{
- if (crtc->state)
+ struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
+
+ if (crtc->state) {
__drm_atomic_helper_crtc_destroy_state(crtc, crtc->state);
- kfree(crtc->state);
+ kfree(s);
+ }
- crtc->state = kzalloc(sizeof(struct rockchip_crtc_state), GFP_KERNEL);
- if (crtc->state)
- crtc->state->crtc = crtc;
+ s = kzalloc(sizeof(*s), GFP_KERNEL);
+ if (!s)
+ return;
+ crtc->state = &s->base;
+ crtc->state->crtc = crtc;
+ s->left_margin = 100;
+ s->right_margin = 100;
+ s->top_margin = 100;
+ s->bottom_margin = 100;
}
static struct drm_crtc_state *vop_crtc_duplicate_state(struct drm_crtc *crtc)
{
- struct rockchip_crtc_state *rockchip_state;
+ struct rockchip_crtc_state *rockchip_state, *old_state;
- rockchip_state = kzalloc(sizeof(*rockchip_state), GFP_KERNEL);
+ old_state = to_rockchip_crtc_state(crtc->state);
+ rockchip_state = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL);
if (!rockchip_state)
return NULL;
kfree(s);
}
+static int vop_crtc_atomic_get_property(struct drm_crtc *crtc,
+ const struct drm_crtc_state *state,
+ struct drm_property *property,
+ uint64_t *val)
+{
+ struct drm_device *drm_dev = crtc->dev;
+ struct drm_mode_config *mode_config = &drm_dev->mode_config;
+ struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
+
+ if (property == mode_config->tv_left_margin_property) {
+ *val = s->left_margin;
+ return 0;
+ }
+
+ if (property == mode_config->tv_right_margin_property) {
+ *val = s->right_margin;
+ return 0;
+ }
+
+ if (property == mode_config->tv_top_margin_property) {
+ *val = s->top_margin;
+ return 0;
+ }
+
+ if (property == mode_config->tv_bottom_margin_property) {
+ *val = s->bottom_margin;
+ return 0;
+ }
+
+ DRM_ERROR("failed to get vop crtc property\n");
+ return -EINVAL;
+}
+
+static int vop_crtc_atomic_set_property(struct drm_crtc *crtc,
+ struct drm_crtc_state *state,
+ struct drm_property *property,
+ uint64_t val)
+{
+ struct drm_device *drm_dev = crtc->dev;
+ struct drm_mode_config *mode_config = &drm_dev->mode_config;
+ struct rockchip_crtc_state *s = to_rockchip_crtc_state(state);
+
+ if (property == mode_config->tv_left_margin_property) {
+ s->left_margin = val;
+ return 0;
+ }
+
+ if (property == mode_config->tv_right_margin_property) {
+ s->right_margin = val;
+ return 0;
+ }
+
+ if (property == mode_config->tv_top_margin_property) {
+ s->top_margin = val;
+ return 0;
+ }
+
+ if (property == mode_config->tv_bottom_margin_property) {
+ s->bottom_margin = val;
+ return 0;
+ }
+
+ DRM_ERROR("failed to set vop crtc property\n");
+ return -EINVAL;
+}
+
static const struct drm_crtc_funcs vop_crtc_funcs = {
.set_config = drm_atomic_helper_set_config,
.page_flip = drm_atomic_helper_page_flip,
.destroy = vop_crtc_destroy,
.reset = vop_crtc_reset,
+ .atomic_get_property = vop_crtc_atomic_get_property,
+ .atomic_set_property = vop_crtc_atomic_set_property,
.atomic_duplicate_state = vop_crtc_duplicate_state,
.atomic_destroy_state = vop_crtc_destroy_state,
};
ret = IRQ_HANDLED;
}
+ if (active_irqs & LINE_FLAG_INTR) {
+ complete(&vop->line_flag_completion);
+ active_irqs &= ~LINE_FLAG_INTR;
+ ret = IRQ_HANDLED;
+ }
+
if (active_irqs & FS_INTR) {
drm_crtc_handle_vblank(crtc);
vop_handle_vblank(vop);
static int vop_create_crtc(struct vop *vop)
{
struct device *dev = vop->dev;
+ const struct vop_data *vop_data = vop->data;
struct drm_device *drm_dev = vop->drm_dev;
struct drm_plane *primary = NULL, *cursor = NULL, *plane, *tmp;
struct drm_crtc *crtc = &vop->crtc;
init_completion(&vop->dsp_hold_completion);
init_completion(&vop->wait_update_complete);
+ init_completion(&vop->line_flag_completion);
crtc->port = port;
rockchip_register_crtc_funcs(crtc, &private_crtc_funcs);
- if (VOP_CTRL_SUPPORT(vop, afbdc_en))
+ ret = drm_mode_create_tv_properties(drm_dev, 0, NULL);
+ if (ret)
+ goto err_unregister_crtc_funcs;
+#define VOP_ATTACH_MODE_CONFIG_PROP(prop, v) \
+ drm_object_attach_property(&crtc->base, drm_dev->mode_config.prop, v)
+
+ VOP_ATTACH_MODE_CONFIG_PROP(tv_left_margin_property, 100);
+ VOP_ATTACH_MODE_CONFIG_PROP(tv_right_margin_property, 100);
+ VOP_ATTACH_MODE_CONFIG_PROP(tv_top_margin_property, 100);
+ VOP_ATTACH_MODE_CONFIG_PROP(tv_bottom_margin_property, 100);
+#undef VOP_ATTACH_MODE_CONFIG_PROP
+
+ if (vop_data->feature & VOP_FEATURE_AFBDC)
feature |= BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC);
drm_object_attach_property(&crtc->base, vop->feature_prop,
feature);
return 0;
+err_unregister_crtc_funcs:
+ rockchip_unregister_crtc_funcs(crtc);
err_cleanup_crtc:
drm_crtc_cleanup(crtc);
err_cleanup_planes:
vop->feature_prop = drm_property_create_bitmask(vop->drm_dev,
DRM_MODE_PROP_IMMUTABLE, "FEATURE",
- props, ARRAY_SIZE(crtc_props),
+ crtc_props, ARRAY_SIZE(crtc_props),
BIT(ROCKCHIP_DRM_CRTC_FEATURE_AFBDC));
if (!vop->feature_prop) {
DRM_ERROR("failed to create vop feature property\n");
return 0;
}
+/**
+ * rockchip_drm_wait_line_flag - acqiure the give line flag event
+ * @crtc: CRTC to enable line flag
+ * @line_num: interested line number
+ * @mstimeout: millisecond for timeout
+ *
+ * Driver would hold here until the interested line flag interrupt have
+ * happened or timeout to wait.
+ *
+ * Returns:
+ * Zero on success, negative errno on failure.
+ */
+int rockchip_drm_wait_line_flag(struct drm_crtc *crtc, unsigned int line_num,
+ unsigned int mstimeout)
+{
+ struct vop *vop = to_vop(crtc);
+ unsigned long jiffies_left;
+
+ if (!crtc || !vop->is_enabled)
+ return -ENODEV;
+
+ if (line_num > crtc->mode.vtotal || mstimeout <= 0)
+ return -EINVAL;
+
+ if (vop_line_flag_irq_is_enabled(vop))
+ return -EBUSY;
+
+ reinit_completion(&vop->line_flag_completion);
+ vop_line_flag_irq_enable(vop, line_num);
+
+ jiffies_left = wait_for_completion_timeout(&vop->line_flag_completion,
+ msecs_to_jiffies(mstimeout));
+ vop_line_flag_irq_disable(vop);
+
+ if (jiffies_left == 0) {
+ dev_err(vop->dev, "Timeout waiting for IRQ\n");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(rockchip_drm_wait_line_flag);
+
static int vop_bind(struct device *dev, struct device *master, void *data)
{
struct platform_device *pdev = to_platform_device(dev);
projects / firefly-linux-kernel-4.4.55.git / blobdiff