}
}
+static bool is_yuv_output(uint32_t bus_format)
+{
+ switch (bus_format) {
+ case MEDIA_BUS_FMT_YUV8_1X24:
+ case MEDIA_BUS_FMT_YUV10_1X30:
+ return true;
+ default:
+ return false;
+ }
+}
+
static bool is_yuv_support(uint32_t format)
{
switch (format) {
if (!win->phy->scl)
return;
- if (dst_w > 3840) {
- DRM_ERROR("Maximum destination width (3840) exceeded\n");
- return;
- }
-
if (!win->phy->scl->ext) {
VOP_SCL_SET(vop, win, scale_yrgb_x,
scl_cal_scale2(src_w, dst_w));
*y2r_table = csc_table->y2r_bt2020;
if (input_csc == CSC_BT2020)
*r2r_table = csc_table->r2r_bt2020_to_bt709;
- if (!is_input_yuv || y2r_table) {
+ if (!is_input_yuv || *y2r_table) {
if (output_csc == CSC_BT709)
*r2y_table = csc_table->r2y_bt709;
else
*r2y_table = csc_table->r2y_bt601;
}
}
-
} else {
if (!is_input_yuv)
return 0;
{
struct vop *vop = to_vop(crtc);
struct drm_atomic_state *state = crtc_state->state;
+ struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
const struct vop_csc_table *csc_table = vop->data->csc_table;
struct drm_plane_state *pstate;
struct drm_plane *plane;
- bool is_yuv;
+ bool is_input_yuv, is_output_yuv;
int ret;
if (!csc_table)
return 0;
+ is_output_yuv = is_yuv_output(s->bus_format);
+
drm_atomic_crtc_state_for_each_plane(plane, crtc_state) {
struct vop_plane_state *vop_plane_state;
if (!pstate->fb)
continue;
- is_yuv = is_yuv_support(pstate->fb->pixel_format);
+ is_input_yuv = is_yuv_support(pstate->fb->pixel_format);
/*
* TODO: force set input and output csc mode.
*/
- ret = vop_csc_setup(csc_table, is_yuv, false,
+ ret = vop_csc_setup(csc_table, is_input_yuv, is_output_yuv,
CSC_BT709, CSC_BT709,
&vop_plane_state->y2r_table,
&vop_plane_state->r2r_table,
spin_unlock_irqrestore(&vop->irq_lock, flags);
}
-static void vop_enable(struct drm_crtc *crtc)
+static void vop_power_enable(struct drm_crtc *crtc)
{
struct vop *vop = to_vop(crtc);
- int ret, i;
+ int ret;
ret = clk_prepare_enable(vop->hclk);
if (ret < 0) {
memcpy(vop->regsbak, vop->regs, vop->len);
- VOP_CTRL_SET(vop, global_regdone_en, 1);
- VOP_CTRL_SET(vop, dsp_blank, 0);
-
- for (i = 0; i < vop->num_wins; i++) {
- struct vop_win *win = &vop->win[i];
-
- VOP_WIN_SET(vop, win, gate, 1);
- }
vop->is_enabled = true;
- spin_lock(&vop->reg_lock);
-
- VOP_CTRL_SET(vop, standby, 0);
-
- spin_unlock(&vop->reg_lock);
-
- enable_irq(vop->irq);
-
- drm_crtc_vblank_on(crtc);
-
return;
err_disable_dclk:
clk_disable_unprepare(vop->hclk);
}
-static void vop_crtc_disable(struct drm_crtc *crtc)
+static void vop_initial(struct drm_crtc *crtc)
{
struct vop *vop = to_vop(crtc);
int i;
+ vop_power_enable(crtc);
+
+ VOP_CTRL_SET(vop, global_regdone_en, 1);
+ VOP_CTRL_SET(vop, dsp_blank, 0);
+
/*
- * We need to make sure that all windows are disabled before we
- * disable that crtc. Otherwise we might try to scan from a destroyed
+ * We need to make sure that all windows are disabled before resume
+ * the crtc. Otherwise we might try to scan from a destroyed
* buffer later.
*/
for (i = 0; i < vop->num_wins; i++) {
struct vop_win *win = &vop->win[i];
+ int channel = i * 2 + 1;
- spin_lock(&vop->reg_lock);
+ VOP_WIN_SET(vop, win, channel, (channel + 1) << 4 | channel);
if (win->phy->scl && win->phy->scl->ext) {
VOP_SCL_SET_EXT(vop, win, yrgb_hor_scl_mode, SCALE_NONE);
VOP_SCL_SET_EXT(vop, win, yrgb_ver_scl_mode, SCALE_NONE);
VOP_SCL_SET_EXT(vop, win, cbcr_ver_scl_mode, SCALE_NONE);
}
VOP_WIN_SET(vop, win, enable, 0);
- spin_unlock(&vop->reg_lock);
+ VOP_WIN_SET(vop, win, gate, 1);
}
VOP_CTRL_SET(vop, afbdc_en, 0);
- vop_cfg_done(vop);
+}
+
+static void vop_crtc_disable(struct drm_crtc *crtc)
+{
+ struct vop *vop = to_vop(crtc);
drm_crtc_vblank_off(crtc);
struct vop_win *win = to_vop_win(plane);
struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
struct drm_crtc_state *crtc_state;
+ const struct vop_data *vop_data;
+ struct vop *vop;
bool visible;
int ret;
struct drm_rect *dest = &vop_plane_state->dest;
DRM_PLANE_HELPER_NO_SCALING;
unsigned long offset;
dma_addr_t dma_addr;
+ u16 vdisplay;
crtc = crtc ? crtc : plane->state->crtc;
/*
dest->x2 = state->crtc_x + state->crtc_w;
dest->y2 = state->crtc_y + state->crtc_h;
+ vdisplay = crtc_state->adjusted_mode.crtc_vdisplay;
+ if (crtc_state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
+ vdisplay *= 2;
+
clip.x1 = 0;
clip.y1 = 0;
- clip.x2 = crtc_state->mode.hdisplay;
- clip.y2 = crtc_state->mode.vdisplay;
+ clip.x2 = crtc_state->adjusted_mode.crtc_hdisplay;
+ clip.y2 = vdisplay;
ret = drm_plane_helper_check_update(plane, crtc, state->fb,
src, dest, &clip,
if (vop_plane_state->format < 0)
return vop_plane_state->format;
+ vop = to_vop(crtc);
+ vop_data = vop->data;
+
+ if (drm_rect_width(src) >> 16 > vop_data->max_input.width ||
+ drm_rect_height(src) >> 16 > vop_data->max_input.height) {
+ DRM_ERROR("Invalid source: %dx%d. max input: %dx%d\n",
+ drm_rect_width(src) >> 16,
+ drm_rect_height(src) >> 16,
+ vop_data->max_input.width,
+ vop_data->max_input.height);
+ return -EINVAL;
+ }
+
/*
* Src.x1 can be odd when do clip, but yuv plane start point
* need align with 2 pixel.
*/
- if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2))
+ if (is_yuv_support(fb->pixel_format) && ((src->x1 >> 16) % 2)) {
+ DRM_ERROR("Invalid Source: Yuv format Can't support odd xpos\n");
return -EINVAL;
+ }
offset = (src->x1 >> 16) * drm_format_plane_bpp(fb->pixel_format, 0) / 8;
if (state->rotation & BIT(DRM_REFLECT_Y))
struct drm_crtc *crtc = state->crtc;
struct vop_win *win = to_vop_win(plane);
struct vop_plane_state *vop_plane_state = to_vop_plane_state(state);
- struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
- struct vop *vop = to_vop(state->crtc);
+ struct rockchip_crtc_state *s;
+ struct vop *vop;
struct drm_framebuffer *fb = state->fb;
unsigned int actual_w, actual_h;
unsigned int dsp_stx, dsp_sty;
ymirror = !!(state->rotation & BIT(DRM_REFLECT_Y));
xmirror = !!(state->rotation & BIT(DRM_REFLECT_X));
+ vop = to_vop(state->crtc);
+ s = to_rockchip_crtc_state(crtc->state);
+
spin_lock(&vop->reg_lock);
VOP_WIN_SET(vop, win, xmirror, xmirror);
if (win->csc) {
vop_load_csc_table(vop, win->csc->y2r_offset, y2r_table);
vop_load_csc_table(vop, win->csc->r2r_offset, r2r_table);
- vop_load_csc_table(vop, win->csc->r2r_offset, r2y_table);
+ vop_load_csc_table(vop, win->csc->r2y_offset, r2y_table);
VOP_WIN_SET_EXT(vop, win, csc, y2r_en, !!y2r_table);
VOP_WIN_SET_EXT(vop, win, csc, r2r_en, !!r2r_table);
VOP_WIN_SET_EXT(vop, win, csc, r2y_en, !!r2y_table);
return 0;
if (on) {
- vop_enable(crtc);
+ vop_power_enable(crtc);
+ enable_irq(vop->irq);
+ drm_crtc_vblank_on(crtc);
vop->loader_protect = true;
} else {
vop_crtc_disable(crtc);
struct drm_framebuffer *fb = state->fb;
int i;
- seq_printf(s, "win%d-%d: status=%s\n", win->win_id, win->area_id,
- pstate->enable ? "active" : "disabled");
+ seq_printf(s, " win%d-%d: %s\n", win->win_id, win->area_id,
+ pstate->enable ? "ACTIVE" : "DISABLED");
if (!fb)
return 0;
src = &pstate->src;
dest = &pstate->dest;
- seq_printf(s, "\tformat: %s\n", drm_get_format_name(fb->pixel_format));
+ seq_printf(s, "\tformat: %s%s\n", drm_get_format_name(fb->pixel_format),
+ fb->modifier[0] == DRM_FORMAT_MOD_ARM_AFBC ? "[AFBC]" : "");
seq_printf(s, "\tzpos: %d\n", pstate->zpos);
seq_printf(s, "\tsrc: pos[%dx%d] rect[%dx%d]\n", src->x1 >> 16,
src->y1 >> 16, drm_rect_width(src) >> 16,
struct vop *vop = to_vop(crtc);
struct drm_crtc_state *crtc_state = crtc->state;
struct drm_display_mode *mode = &crtc->state->adjusted_mode;
+ struct rockchip_crtc_state *state = to_rockchip_crtc_state(crtc->state);
+ bool interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
struct drm_plane *plane;
int i;
- seq_printf(s, "vop name: %s status=%s\n", dev_name(vop->dev),
- crtc_state->active ? "active" : "disabled");
+ seq_printf(s, "VOP [%s]: %s\n", dev_name(vop->dev),
+ crtc_state->active ? "ACTIVE" : "DISABLED");
if (!crtc_state->active)
return 0;
- seq_printf(s, "Display mode: %s fps[%d] clk[%d] type[%d] flag[%x]\n",
- mode->name, drm_mode_vrefresh(mode), mode->clock,
- mode->type, mode->flags);
+ seq_printf(s, " Connector: %s\n",
+ drm_get_connector_name(state->output_type));
+ seq_printf(s, "\tbus_format[%x] output_mode[%x]\n",
+ state->bus_format, state->output_mode);
+ seq_printf(s, " Display mode: %dx%d%s%d\n",
+ mode->hdisplay, mode->vdisplay, interlaced ? "i" : "p",
+ drm_mode_vrefresh(mode));
+ seq_printf(s, "\tclk[%d] real_clk[%d] type[%x] flag[%x]\n",
+ mode->clock, mode->crtc_clock, mode->type, mode->flags);
seq_printf(s, "\tH: %d %d %d %d\n", mode->hdisplay, mode->hsync_start,
mode->hsync_end, mode->htotal);
seq_printf(s, "\tV: %d %d %d %d\n", mode->vdisplay, mode->vsync_start,
return 0;
}
+static enum drm_mode_status
+vop_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode,
+ int output_type)
+{
+ struct vop *vop = to_vop(crtc);
+ const struct vop_data *vop_data = vop->data;
+ int request_clock = mode->clock;
+ int clock;
+
+ if (mode->hdisplay > vop_data->max_output.width)
+ return MODE_BAD_HVALUE;
+ if (mode->vdisplay > vop_data->max_output.height)
+ return MODE_BAD_VVALUE;
+
+ if (mode->flags & DRM_MODE_FLAG_DBLCLK)
+ request_clock *= 2;
+ clock = clk_round_rate(vop->dclk, request_clock * 1000) / 1000;
+
+ /*
+ * Hdmi or DisplayPort request a Accurate clock.
+ */
+ if (output_type == DRM_MODE_CONNECTOR_HDMIA ||
+ output_type == DRM_MODE_CONNECTOR_DisplayPort)
+ if (clock != request_clock)
+ return MODE_CLOCK_RANGE;
+
+ return MODE_OK;
+}
+
static const struct rockchip_crtc_funcs private_crtc_funcs = {
.loader_protect = vop_crtc_loader_protect,
.enable_vblank = vop_crtc_enable_vblank,
.wait_for_update = vop_crtc_wait_for_update,
.cancel_pending_vblank = vop_crtc_cancel_pending_vblank,
.debugfs_dump = vop_crtc_debugfs_dump,
+ .mode_valid = vop_crtc_mode_valid,
};
static bool vop_crtc_mode_fixup(struct drm_crtc *crtc,
const struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode)
+ struct drm_display_mode *adj_mode)
{
struct vop *vop = to_vop(crtc);
+ const struct vop_data *vop_data = vop->data;
+
+ if (mode->hdisplay > vop_data->max_output.width ||
+ mode->vdisplay > vop_data->max_output.height)
+ return false;
+
+ drm_mode_set_crtcinfo(adj_mode,
+ CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE);
+
+ if (mode->flags & DRM_MODE_FLAG_DBLCLK)
+ adj_mode->crtc_clock *= 2;
- adjusted_mode->clock =
- clk_round_rate(vop->dclk, mode->clock * 1000) / 1000;
+ adj_mode->crtc_clock =
+ clk_round_rate(vop->dclk, adj_mode->crtc_clock * 1000) / 1000;
return true;
}
u16 vsync_len = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
u16 vact_st = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start;
u16 vact_end = vact_st + vdisplay;
- uint32_t version = vop->data->version;
uint32_t val;
- vop_enable(crtc);
- /*
- * If dclk rate is zero, mean that scanout is stop,
- * we don't need wait any more.
- *
- * Since vop version(3,4), vop timing is frame effect, not need config
- * timing register on vblank.
- */
- if (clk_get_rate(vop->dclk) &&
- !(VOP_MAJOR(version) == 3 && VOP_MINOR(version) >= 4)) {
- /*
- * Rk3288 vop timing register is immediately, when configure
- * display timing on display time, may cause tearing.
- *
- * Vop standby will take effect at end of current frame,
- * if dsp hold valid irq happen, it means standby complete.
- *
- * mode set:
- * standby and wait complete --> |----
- * | display time
- * |----
- * |---> dsp hold irq
- * configure display timing --> |
- * standby exit |
- * | new frame start.
- */
-
- reinit_completion(&vop->dsp_hold_completion);
- vop_dsp_hold_valid_irq_enable(vop);
-
- spin_lock(&vop->reg_lock);
-
- VOP_CTRL_SET(vop, standby, 1);
-
- spin_unlock(&vop->reg_lock);
-
- WARN_ON(!wait_for_completion_timeout(&vop->dsp_hold_completion,
- msecs_to_jiffies(50)));
-
- vop_dsp_hold_valid_irq_disable(vop);
- }
+ vop_initial(crtc);
val = BIT(DCLK_INVERT);
val |= (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) ?
case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
val = DITHER_DOWN_EN(1) | DITHER_DOWN_MODE(RGB888_TO_RGB666);
break;
+ case MEDIA_BUS_FMT_YUV8_1X24:
+ val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(1);
+ break;
+ case MEDIA_BUS_FMT_YUV10_1X30:
+ val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
+ break;
case MEDIA_BUS_FMT_RGB888_1X24:
default:
val = DITHER_DOWN_EN(0) | PRE_DITHER_DOWN_EN(0);
break;
}
+
if (s->output_mode == ROCKCHIP_OUT_MODE_AAAA)
val |= PRE_DITHER_DOWN_EN(0);
else
val |= PRE_DITHER_DOWN_EN(1);
val |= DITHER_DOWN_MODE_SEL(DITHER_DOWN_ALLEGRO);
VOP_CTRL_SET(vop, dither_down, val);
+ VOP_CTRL_SET(vop, dclk_ddr,
+ s->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0);
+ VOP_CTRL_SET(vop, overlay_mode, is_yuv_output(s->bus_format));
+ VOP_CTRL_SET(vop, dsp_out_yuv, is_yuv_output(s->bus_format));
+ VOP_CTRL_SET(vop, dsp_background,
+ is_yuv_output(s->bus_format) ? 0x20010200 : 0);
VOP_CTRL_SET(vop, htotal_pw, (htotal << 16) | hsync_len);
val = hact_st << 16;
VOP_CTRL_SET(vop, hact_st_end, val);
VOP_CTRL_SET(vop, hpost_st_end, val);
- VOP_CTRL_SET(vop, vtotal_pw, (adjusted_mode->vtotal << 16) | vsync_len);
val = vact_st << 16;
val |= vact_end;
VOP_CTRL_SET(vop, vact_st_end, val);
VOP_CTRL_SET(vop, vs_st_end_f1, val);
VOP_CTRL_SET(vop, dsp_interlace, 1);
VOP_CTRL_SET(vop, p2i_en, 1);
+ vtotal += vtotal + 1;
} else {
VOP_CTRL_SET(vop, dsp_interlace, 0);
VOP_CTRL_SET(vop, p2i_en, 0);
}
+ VOP_CTRL_SET(vop, vtotal_pw, vtotal << 16 | vsync_len);
+
+ VOP_CTRL_SET(vop, core_dclk_div,
+ !!(adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK));
- clk_set_rate(vop->dclk, adjusted_mode->clock * 1000);
+ clk_set_rate(vop->dclk, adjusted_mode->crtc_clock * 1000);
+ vop_cfg_done(vop);
+ /*
+ * enable vop, all the register would take effect when vop exit standby
+ */
VOP_CTRL_SET(vop, standby, 0);
+
+ enable_irq(vop->irq);
+ drm_crtc_vblank_on(crtc);
}
static int vop_zpos_cmp(const void *a, const void *b)
projects / firefly-linux-kernel-4.4.55.git / blobdiff