drm/rockchip: vop: add rk3366 vop lit support

[firefly-linux-kernel-4.4.55.git] / drivers / gpu / drm / rockchip / rockchip_drm_vop.h

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index 9e912415f800304864639a40280a4c06e156ee24..0782d1b3fb297719450c190da8f7e6491e8e0278 100644 (file)
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -27,6 +27,17 @@
 #define AFBDC_FMT_U8U8U8U8     0x5
 #define AFBDC_FMT_U8U8U8       0x4
 
+enum cabc_stage_mode {
+       LAST_FRAME_PWM_VAL      = 0x0,
+       CUR_FRAME_PWM_VAL       = 0x1,
+       STAGE_BY_STAGE          = 0x2
+};
+
+enum cabc_stage_up_mode {
+       MUL_MODE,
+       ADD_MODE,
+};
+
 enum vop_csc_format {
        CSC_BT601,
        CSC_BT709,
@@ -95,20 +106,34 @@ struct vop_ctrl {
        struct vop_reg dclk_ddr;
        struct vop_reg p2i_en;
        struct vop_reg rgb_en;
+       struct vop_reg lvds_en;
        struct vop_reg edp_en;
        struct vop_reg hdmi_en;
        struct vop_reg mipi_en;
        struct vop_reg dp_en;
+       struct vop_reg dclk_pol;
        struct vop_reg pin_pol;
+       struct vop_reg rgb_dclk_pol;
        struct vop_reg rgb_pin_pol;
+       struct vop_reg lvds_dclk_pol;
+       struct vop_reg lvds_pin_pol;
+       struct vop_reg hdmi_dclk_pol;
        struct vop_reg hdmi_pin_pol;
+       struct vop_reg edp_dclk_pol;
        struct vop_reg edp_pin_pol;
+       struct vop_reg mipi_dclk_pol;
        struct vop_reg mipi_pin_pol;
+       struct vop_reg dp_dclk_pol;
        struct vop_reg dp_pin_pol;
-
        struct vop_reg dither_up;
        struct vop_reg dither_down;
 
+       struct vop_reg sw_dac_sel;
+       struct vop_reg tve_sw_mode;
+       struct vop_reg tve_dclk_pol;
+       struct vop_reg tve_dclk_en;
+       struct vop_reg sw_genlock;
+       struct vop_reg sw_uv_offset_en;
        struct vop_reg dsp_out_yuv;
        struct vop_reg dsp_data_swap;
        struct vop_reg dsp_ccir656_avg;
@@ -134,6 +159,21 @@ struct vop_ctrl {
        struct vop_reg afbdc_hdr_ptr;
        struct vop_reg afbdc_rstn;
 
+       /* CABC */
+       struct vop_reg cabc_total_num;
+       struct vop_reg cabc_config_mode;
+       struct vop_reg cabc_stage_up_mode;
+       struct vop_reg cabc_scale_cfg_value;
+       struct vop_reg cabc_scale_cfg_enable;
+       struct vop_reg cabc_global_dn_limit_en;
+       struct vop_reg cabc_lut_en;
+       struct vop_reg cabc_en;
+       struct vop_reg cabc_handle_en;
+       struct vop_reg cabc_stage_up;
+       struct vop_reg cabc_stage_down;
+       struct vop_reg cabc_global_dn;
+       struct vop_reg cabc_calc_pixel_num;
+
        struct vop_reg cfg_done;
 };
 
@@ -277,6 +317,8 @@ struct vop_data {
        u64 feature;
 };
 
+#define CVBS_PAL_VDISPLAY              288
+
 /* interrupt define */
 #define DSP_HOLD_VALID_INTR            (1 << 0)
 #define FS_INTR                                (1 << 1)
@@ -419,7 +461,6 @@ enum vop_pol {
        HSYNC_POSITIVE = 0,
        VSYNC_POSITIVE = 1,
        DEN_NEGATIVE   = 2,
-       DCLK_INVERT    = 3
 };
 
 #define FRAC_16_16(mult, div)    (((mult) << 16) / (div))