drm/rockchip: vop: add rk3366 vop lit support

[firefly-linux-kernel-4.4.55.git] / drivers / gpu / drm / rockchip / rockchip_drm_vop.h

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index de9685093aca917217f9d1be71f8d90fbe515943..0782d1b3fb297719450c190da8f7e6491e8e0278 100644 (file)
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -27,6 +27,17 @@
 #define AFBDC_FMT_U8U8U8U8     0x5
 #define AFBDC_FMT_U8U8U8       0x4
 
+enum cabc_stage_mode {
+       LAST_FRAME_PWM_VAL      = 0x0,
+       CUR_FRAME_PWM_VAL       = 0x1,
+       STAGE_BY_STAGE          = 0x2
+};
+
+enum cabc_stage_up_mode {
+       MUL_MODE,
+       ADD_MODE,
+};
+
 enum vop_csc_format {
        CSC_BT601,
        CSC_BT709,
@@ -92,27 +103,45 @@ struct vop_ctrl {
        struct vop_reg dsp_layer_sel;
        struct vop_reg overlay_mode;
        struct vop_reg core_dclk_div;
+       struct vop_reg dclk_ddr;
        struct vop_reg p2i_en;
        struct vop_reg rgb_en;
+       struct vop_reg lvds_en;
        struct vop_reg edp_en;
        struct vop_reg hdmi_en;
        struct vop_reg mipi_en;
        struct vop_reg dp_en;
+       struct vop_reg dclk_pol;
        struct vop_reg pin_pol;
+       struct vop_reg rgb_dclk_pol;
        struct vop_reg rgb_pin_pol;
+       struct vop_reg lvds_dclk_pol;
+       struct vop_reg lvds_pin_pol;
+       struct vop_reg hdmi_dclk_pol;
        struct vop_reg hdmi_pin_pol;
+       struct vop_reg edp_dclk_pol;
        struct vop_reg edp_pin_pol;
+       struct vop_reg mipi_dclk_pol;
        struct vop_reg mipi_pin_pol;
+       struct vop_reg dp_dclk_pol;
        struct vop_reg dp_pin_pol;
-
        struct vop_reg dither_up;
        struct vop_reg dither_down;
 
+       struct vop_reg sw_dac_sel;
+       struct vop_reg tve_sw_mode;
+       struct vop_reg tve_dclk_pol;
+       struct vop_reg tve_dclk_en;
+       struct vop_reg sw_genlock;
+       struct vop_reg sw_uv_offset_en;
+       struct vop_reg dsp_out_yuv;
        struct vop_reg dsp_data_swap;
        struct vop_reg dsp_ccir656_avg;
        struct vop_reg dsp_black;
        struct vop_reg dsp_blank;
        struct vop_reg dsp_outzero;
+       struct vop_reg update_gamma_lut;
+       struct vop_reg lut_buffer_index;
        struct vop_reg dsp_lut_en;
 
        struct vop_reg out_mode;
@@ -130,6 +159,21 @@ struct vop_ctrl {
        struct vop_reg afbdc_hdr_ptr;
        struct vop_reg afbdc_rstn;
 
+       /* CABC */
+       struct vop_reg cabc_total_num;
+       struct vop_reg cabc_config_mode;
+       struct vop_reg cabc_stage_up_mode;
+       struct vop_reg cabc_scale_cfg_value;
+       struct vop_reg cabc_scale_cfg_enable;
+       struct vop_reg cabc_global_dn_limit_en;
+       struct vop_reg cabc_lut_en;
+       struct vop_reg cabc_en;
+       struct vop_reg cabc_handle_en;
+       struct vop_reg cabc_stage_up;
+       struct vop_reg cabc_stage_down;
+       struct vop_reg cabc_global_dn;
+       struct vop_reg cabc_calc_pixel_num;
+
        struct vop_reg cfg_done;
 };
 
@@ -208,6 +252,11 @@ enum {
        VOP_CSC_R2R_BT709_TO_2020,
 };
 
+enum _vop_overlay_mode {
+       VOP_RGB_DOMAIN,
+       VOP_YUV_DOMAIN
+};
+
 struct vop_win_phy {
        const struct vop_scl_regs *scl;
        const uint32_t *data_formats;
@@ -228,6 +277,7 @@ struct vop_win_phy {
        struct vop_reg yrgb_vir;
        struct vop_reg uv_vir;
 
+       struct vop_reg channel;
        struct vop_reg dst_alpha_ctl;
        struct vop_reg src_alpha_ctl;
        struct vop_reg alpha_mode;
@@ -248,6 +298,11 @@ struct vop_win_data {
 #define VOP_FEATURE_OUTPUT_10BIT       BIT(0)
 #define VOP_FEATURE_AFBDC              BIT(1)
 
+struct vop_rect {
+       int width;
+       int height;
+};
+
 struct vop_data {
        const struct vop_reg_data *init_table;
        unsigned int table_size;
@@ -257,9 +312,13 @@ struct vop_data {
        const struct vop_csc_table *csc_table;
        unsigned int win_size;
        uint32_t version;
+       struct vop_rect max_input;
+       struct vop_rect max_output;
        u64 feature;
 };
 
+#define CVBS_PAL_VDISPLAY              288
+
 /* interrupt define */
 #define DSP_HOLD_VALID_INTR            (1 << 0)
 #define FS_INTR                                (1 << 1)
@@ -316,11 +375,12 @@ struct vop_data {
 /*
  * display output interface supported by rockchip lcdc
  */
-#define ROCKCHIP_OUT_MODE_P888 0
-#define ROCKCHIP_OUT_MODE_P666 1
-#define ROCKCHIP_OUT_MODE_P565 2
+#define ROCKCHIP_OUT_MODE_P888         0
+#define ROCKCHIP_OUT_MODE_P666         1
+#define ROCKCHIP_OUT_MODE_P565         2
+#define ROCKCHIP_OUT_MODE_YUV420       14
 /* for use special outface */
-#define ROCKCHIP_OUT_MODE_AAAA 15
+#define ROCKCHIP_OUT_MODE_AAAA         15
 
 #define ROCKCHIP_OUT_MODE_TYPE(x)      ((x) >> 16)
 #define ROCKCHIP_OUT_MODE(x)           ((x) & 0xffff)
@@ -401,7 +461,6 @@ enum vop_pol {
        HSYNC_POSITIVE = 0,
        VSYNC_POSITIVE = 1,
        DEN_NEGATIVE   = 2,
-       DCLK_INVERT    = 3
 };
 
 #define FRAC_16_16(mult, div)    (((mult) << 16) / (div))
@@ -430,6 +489,9 @@ static inline uint16_t scl_get_bili_dn_vskip(int src_h, int dst_h,
 
        act_height = (src_h + vskiplines - 1) / vskiplines;
 
+       if (act_height == dst_h)
+               return GET_SCL_FT_BILI_DN(src_h, dst_h) / vskiplines;
+
        return GET_SCL_FT_BILI_DN(act_height, dst_h);
 }
 
@@ -472,5 +534,10 @@ static inline int scl_vop_cal_lb_mode(int width, bool is_yuv)
        return lb_mode;
 }
 
+static inline int us_to_vertical_line(struct drm_display_mode *mode, int us)
+{
+       return us * mode->clock / mode->htotal / 1000;
+}
+
 extern const struct component_ops vop_component_ops;
 #endif /* _ROCKCHIP_DRM_VOP_H */