#ifndef _ROCKCHIP_DRM_VOP_H
#define _ROCKCHIP_DRM_VOP_H
+/*
+ * major: IP major vertion, used for IP structure
+ * minor: big feature change under same structure
+ */
+#define VOP_VERSION(major, minor) ((major) << 8 | (minor))
+#define VOP_MAJOR(version) ((version) >> 8)
+#define VOP_MINOR(version) ((version) & 0xff)
+
+#define AFBDC_FMT_RGB565 0x0
+#define AFBDC_FMT_U8U8U8U8 0x5
+#define AFBDC_FMT_U8U8U8 0x4
+
+enum cabc_stage_mode {
+ LAST_FRAME_PWM_VAL = 0x0,
+ CUR_FRAME_PWM_VAL = 0x1,
+ STAGE_BY_STAGE = 0x2
+};
+
+enum cabc_stage_up_mode {
+ MUL_MODE,
+ ADD_MODE,
+};
+
+enum vop_csc_format {
+ CSC_BT601,
+ CSC_BT709,
+ CSC_BT2020,
+};
+
+enum vop_csc_mode {
+ CSC_RGB,
+ CSC_YUV,
+};
+
enum vop_data_format {
VOP_FMT_ARGB8888 = 0,
VOP_FMT_RGB888,
};
struct vop_reg {
- uint32_t offset;
- uint32_t shift;
uint32_t mask;
- bool write_mask;
+ uint32_t offset:12;
+ uint32_t shift:5;
+ uint32_t begin_minor:4;
+ uint32_t end_minor:4;
+ uint32_t major:3;
+ uint32_t write_mask:1;
+};
+
+struct vop_csc {
+ struct vop_reg y2r_en;
+ struct vop_reg r2r_en;
+ struct vop_reg r2y_en;
+
+ uint32_t y2r_offset;
+ uint32_t r2r_offset;
+ uint32_t r2y_offset;
};
struct vop_ctrl {
struct vop_reg standby;
- struct vop_reg data_blank;
- struct vop_reg gate_en;
- struct vop_reg mmu_en;
+ struct vop_reg htotal_pw;
+ struct vop_reg hact_st_end;
+ struct vop_reg vtotal_pw;
+ struct vop_reg vact_st_end;
+ struct vop_reg vact_st_end_f1;
+ struct vop_reg vs_st_end_f1;
+ struct vop_reg hpost_st_end;
+ struct vop_reg vpost_st_end;
+ struct vop_reg vpost_st_end_f1;
+ struct vop_reg post_scl_factor;
+ struct vop_reg post_scl_ctrl;
+ struct vop_reg dsp_interlace;
+ struct vop_reg global_regdone_en;
+ struct vop_reg auto_gate_en;
+ struct vop_reg post_lb_mode;
+ struct vop_reg dsp_layer_sel;
+ struct vop_reg overlay_mode;
+ struct vop_reg core_dclk_div;
+ struct vop_reg dclk_ddr;
+ struct vop_reg p2i_en;
struct vop_reg rgb_en;
+ struct vop_reg lvds_en;
struct vop_reg edp_en;
struct vop_reg hdmi_en;
struct vop_reg mipi_en;
- struct vop_reg out_mode;
- struct vop_reg dsp_layer_sel;
- struct vop_reg dither_down;
- struct vop_reg dither_up;
+ struct vop_reg dp_en;
+ struct vop_reg dclk_pol;
struct vop_reg pin_pol;
+ struct vop_reg rgb_dclk_pol;
struct vop_reg rgb_pin_pol;
+ struct vop_reg lvds_dclk_pol;
+ struct vop_reg lvds_pin_pol;
+ struct vop_reg hdmi_dclk_pol;
struct vop_reg hdmi_pin_pol;
+ struct vop_reg edp_dclk_pol;
struct vop_reg edp_pin_pol;
+ struct vop_reg mipi_dclk_pol;
struct vop_reg mipi_pin_pol;
+ struct vop_reg dp_dclk_pol;
+ struct vop_reg dp_pin_pol;
+ struct vop_reg dither_up;
+ struct vop_reg dither_down;
- struct vop_reg htotal_pw;
- struct vop_reg hact_st_end;
- struct vop_reg vtotal_pw;
- struct vop_reg vact_st_end;
- struct vop_reg hpost_st_end;
- struct vop_reg vpost_st_end;
+ struct vop_reg sw_dac_sel;
+ struct vop_reg tve_sw_mode;
+ struct vop_reg tve_dclk_pol;
+ struct vop_reg tve_dclk_en;
+ struct vop_reg sw_genlock;
+ struct vop_reg sw_uv_offset_en;
+ struct vop_reg dsp_out_yuv;
+ struct vop_reg dsp_data_swap;
+ struct vop_reg dsp_ccir656_avg;
+ struct vop_reg dsp_black;
+ struct vop_reg dsp_blank;
+ struct vop_reg dsp_outzero;
+ struct vop_reg update_gamma_lut;
+ struct vop_reg lut_buffer_index;
+ struct vop_reg dsp_lut_en;
+
+ struct vop_reg out_mode;
+
+ struct vop_reg xmirror;
+ struct vop_reg ymirror;
+ struct vop_reg dsp_background;
+
+ /* AFBDC */
+ struct vop_reg afbdc_en;
+ struct vop_reg afbdc_sel;
+ struct vop_reg afbdc_format;
+ struct vop_reg afbdc_hreg_block_split;
+ struct vop_reg afbdc_pic_size;
+ struct vop_reg afbdc_hdr_ptr;
+ struct vop_reg afbdc_rstn;
+
+ /* CABC */
+ struct vop_reg cabc_total_num;
+ struct vop_reg cabc_config_mode;
+ struct vop_reg cabc_stage_up_mode;
+ struct vop_reg cabc_scale_cfg_value;
+ struct vop_reg cabc_scale_cfg_enable;
+ struct vop_reg cabc_global_dn_limit_en;
+ struct vop_reg cabc_lut_en;
+ struct vop_reg cabc_en;
+ struct vop_reg cabc_handle_en;
+ struct vop_reg cabc_stage_up;
+ struct vop_reg cabc_stage_down;
+ struct vop_reg cabc_global_dn;
+ struct vop_reg cabc_calc_pixel_num;
struct vop_reg cfg_done;
};
struct vop_intr {
const int *intrs;
uint32_t nintrs;
+ struct vop_reg line_flag_num[2];
struct vop_reg enable;
struct vop_reg clear;
struct vop_reg status;
struct vop_reg scale_cbcr_y;
};
+struct vop_csc_table {
+ const uint32_t *y2r_bt601;
+ const uint32_t *y2r_bt601_12_235;
+ const uint32_t *y2r_bt601_10bit;
+ const uint32_t *y2r_bt601_10bit_12_235;
+ const uint32_t *r2y_bt601;
+ const uint32_t *r2y_bt601_12_235;
+ const uint32_t *r2y_bt601_10bit;
+ const uint32_t *r2y_bt601_10bit_12_235;
+
+ const uint32_t *y2r_bt709;
+ const uint32_t *y2r_bt709_10bit;
+ const uint32_t *r2y_bt709;
+ const uint32_t *r2y_bt709_10bit;
+
+ const uint32_t *y2r_bt2020;
+ const uint32_t *r2y_bt2020;
+
+ const uint32_t *r2r_bt709_to_bt2020;
+ const uint32_t *r2r_bt2020_to_bt709;
+};
+
+enum {
+ VOP_CSC_Y2R_BT601,
+ VOP_CSC_Y2R_BT709,
+ VOP_CSC_Y2R_BT2020,
+ VOP_CSC_R2Y_BT601,
+ VOP_CSC_R2Y_BT709,
+ VOP_CSC_R2Y_BT2020,
+ VOP_CSC_R2R_BT2020_TO_BT709,
+ VOP_CSC_R2R_BT709_TO_2020,
+};
+
+enum _vop_overlay_mode {
+ VOP_RGB_DOMAIN,
+ VOP_YUV_DOMAIN
+};
+
struct vop_win_phy {
const struct vop_scl_regs *scl;
const uint32_t *data_formats;
uint32_t nformats;
+ struct vop_reg gate;
struct vop_reg enable;
struct vop_reg format;
+ struct vop_reg fmt_10;
+ struct vop_reg xmirror;
+ struct vop_reg ymirror;
struct vop_reg rb_swap;
struct vop_reg act_info;
struct vop_reg dsp_info;
struct vop_reg yrgb_vir;
struct vop_reg uv_vir;
+ struct vop_reg channel;
struct vop_reg dst_alpha_ctl;
struct vop_reg src_alpha_ctl;
+ struct vop_reg alpha_mode;
+ struct vop_reg alpha_en;
+ struct vop_reg key_color;
+ struct vop_reg key_en;
};
struct vop_win_data {
enum drm_plane_type type;
const struct vop_win_phy *phy;
const struct vop_win_phy **area;
+ const struct vop_csc *csc;
unsigned int area_size;
};
-#define VOP_FEATURE_OUTPUT_10BIT BIT(0)
+#define VOP_FEATURE_OUTPUT_10BIT BIT(0)
+#define VOP_FEATURE_AFBDC BIT(1)
+
+struct vop_rect {
+ int width;
+ int height;
+};
struct vop_data {
const struct vop_reg_data *init_table;
const struct vop_ctrl *ctrl;
const struct vop_intr *intr;
const struct vop_win_data *win;
+ const struct vop_csc_table *csc_table;
unsigned int win_size;
+ uint32_t version;
+ struct vop_rect max_input;
+ struct vop_rect max_output;
u64 feature;
};
+#define CVBS_PAL_VDISPLAY 288
+
/* interrupt define */
#define DSP_HOLD_VALID_INTR (1 << 0)
#define FS_INTR (1 << 1)
#define LINE_FLAG_INTR (1 << 2)
#define BUS_ERROR_INTR (1 << 3)
+#define FS_NEW_INTR (1 << 4)
+#define ADDR_SAME_INTR (1 << 5)
+#define LINE_FLAG1_INTR (1 << 6)
+#define WIN0_EMPTY_INTR (1 << 7)
+#define WIN1_EMPTY_INTR (1 << 8)
+#define WIN2_EMPTY_INTR (1 << 9)
+#define WIN3_EMPTY_INTR (1 << 10)
+#define HWC_EMPTY_INTR (1 << 11)
+#define POST_BUF_EMPTY_INTR (1 << 12)
+#define PWM_GEN_INTR (1 << 13)
#define INTR_MASK (DSP_HOLD_VALID_INTR | FS_INTR | \
- LINE_FLAG_INTR | BUS_ERROR_INTR)
+ LINE_FLAG_INTR | BUS_ERROR_INTR | \
+ FS_NEW_INTR | LINE_FLAG1_INTR | \
+ WIN0_EMPTY_INTR | WIN1_EMPTY_INTR | \
+ WIN2_EMPTY_INTR | WIN3_EMPTY_INTR | \
+ HWC_EMPTY_INTR | POST_BUF_EMPTY_INTR)
#define DSP_HOLD_VALID_INTR_EN(x) ((x) << 4)
#define FS_INTR_EN(x) ((x) << 5)
/*
* display output interface supported by rockchip lcdc
*/
-#define ROCKCHIP_OUT_MODE_P888 0
-#define ROCKCHIP_OUT_MODE_P666 1
-#define ROCKCHIP_OUT_MODE_P565 2
+#define ROCKCHIP_OUT_MODE_P888 0
+#define ROCKCHIP_OUT_MODE_P666 1
+#define ROCKCHIP_OUT_MODE_P565 2
+#define ROCKCHIP_OUT_MODE_YUV420 14
/* for use special outface */
-#define ROCKCHIP_OUT_MODE_AAAA 15
+#define ROCKCHIP_OUT_MODE_AAAA 15
#define ROCKCHIP_OUT_MODE_TYPE(x) ((x) >> 16)
#define ROCKCHIP_OUT_MODE(x) ((x) & 0xffff)
SCALE_DOWN_AVG = 0x1
};
+enum dither_down_mode {
+ RGB888_TO_RGB565 = 0x0,
+ RGB888_TO_RGB666 = 0x1
+};
+
+enum dither_down_mode_sel {
+ DITHER_DOWN_ALLEGRO = 0x0,
+ DITHER_DOWN_FRC = 0x1
+};
+
+#define PRE_DITHER_DOWN_EN(x) ((x) << 0)
+#define DITHER_DOWN_EN(x) ((x) << 1)
+#define DITHER_DOWN_MODE(x) ((x) << 2)
+#define DITHER_DOWN_MODE_SEL(x) ((x) << 3)
+
+enum vop_pol {
+ HSYNC_POSITIVE = 0,
+ VSYNC_POSITIVE = 1,
+ DEN_NEGATIVE = 2,
+};
+
#define FRAC_16_16(mult, div) (((mult) << 16) / (div))
#define SCL_FT_DEFAULT_FIXPOINT_SHIFT 12
#define SCL_MAX_VSKIPLINES 4
act_height = (src_h + vskiplines - 1) / vskiplines;
+ if (act_height == dst_h)
+ return GET_SCL_FT_BILI_DN(src_h, dst_h) / vskiplines;
+
return GET_SCL_FT_BILI_DN(act_height, dst_h);
}
return lb_mode;
}
+static inline int us_to_vertical_line(struct drm_display_mode *mode, int us)
+{
+ return us * mode->clock / mode->htotal / 1000;
+}
+
extern const struct component_ops vop_component_ops;
#endif /* _ROCKCHIP_DRM_VOP_H */
projects / firefly-linux-kernel-4.4.55.git / blobdiff