#include <linux/platform_device.h>
#include <linux/hwmon.h>
#include <linux/hwmon-sysfs.h>
+#include <linux/hwmon-vid.h>
#include <linux/err.h>
#include <linux/mutex.h>
#include <asm/io.h>
#define SIO_REG_LDSEL 0x07 /* Logical device select */
#define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */
+#define SIO_REG_EN_VRM10 0x2C /* GPIO3, GPIO4 selection */
#define SIO_REG_ENABLE 0x30 /* Logical device enable */
#define SIO_REG_ADDR 0x60 /* Logical device address (2 bytes) */
+#define SIO_REG_VID_CTRL 0xF0 /* VID control */
+#define SIO_REG_VID_DATA 0xF1 /* VID data */
#define SIO_W83627EHF_ID 0x8850
#define SIO_W83627EHG_ID 0x8860
u8 fan_min[5];
u8 fan_div[5];
u8 has_fan; /* some fan inputs can be disabled */
+ u8 temp_type[3];
s8 temp1;
s8 temp1_max;
s8 temp1_max_hyst;
u8 fan_min_output[4]; /* minimum fan speed */
u8 fan_stop_time[4];
+
+ u8 vid;
+ u8 vrm;
};
struct w83627ehf_sio_data {
mutex_lock(&data->update_lock);
- if (time_after(jiffies, data->last_updated + HZ)
+ if (time_after(jiffies, data->last_updated + HZ + HZ/2)
|| !data->valid) {
/* Fan clock dividers */
i = w83627ehf_read_value(data, W83627EHF_REG_FANDIV1);
div_from_reg(new_div));
data->fan_div[nr] = new_div;
w83627ehf_write_fan_div(data, nr);
+ /* Give the chip time to sample a new speed value */
+ data->last_updated = jiffies;
}
w83627ehf_write_value(data, W83627EHF_REG_FAN_MIN[nr],
data->fan_min[nr]);
store_temp_reg(OVER, temp_max);
store_temp_reg(HYST, temp_max_hyst);
+static ssize_t
+show_temp_type(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct w83627ehf_data *data = w83627ehf_update_device(dev);
+ struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
+ int nr = sensor_attr->index;
+ return sprintf(buf, "%d\n", (int)data->temp_type[nr]);
+}
+
static struct sensor_device_attribute sda_temp[] = {
SENSOR_ATTR(temp1_input, S_IRUGO, show_temp1, NULL, 0),
SENSOR_ATTR(temp2_input, S_IRUGO, show_temp, NULL, 0),
SENSOR_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 4),
SENSOR_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 5),
SENSOR_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 13),
+ SENSOR_ATTR(temp1_type, S_IRUGO, show_temp_type, NULL, 0),
+ SENSOR_ATTR(temp2_type, S_IRUGO, show_temp_type, NULL, 1),
+ SENSOR_ATTR(temp3_type, S_IRUGO, show_temp_type, NULL, 2),
};
#define show_pwm_reg(reg) \
store_fan_min_output, 2),
};
+static ssize_t
+show_vid(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct w83627ehf_data *data = dev_get_drvdata(dev);
+ return sprintf(buf, "%d\n", vid_from_reg(data->vid, data->vrm));
+}
+static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid, NULL);
+
/*
* Driver and device management
*/
device_remove_file(dev, &sda_temp[i].dev_attr);
device_remove_file(dev, &dev_attr_name);
+ if (data->vid != 0x3f)
+ device_remove_file(dev, &dev_attr_cpu0_vid);
}
/* Get the monitoring functions started */
static inline void __devinit w83627ehf_init_device(struct w83627ehf_data *data)
{
int i;
- u8 tmp;
+ u8 tmp, diode;
/* Start monitoring is needed */
tmp = w83627ehf_read_value(data, W83627EHF_REG_CONFIG);
W83627EHF_REG_TEMP_CONFIG[i],
tmp & 0xfe);
}
+
+ /* Enable VBAT monitoring if needed */
+ tmp = w83627ehf_read_value(data, W83627EHF_REG_VBAT);
+ if (!(tmp & 0x01))
+ w83627ehf_write_value(data, W83627EHF_REG_VBAT, tmp | 0x01);
+
+ /* Get thermal sensor types */
+ diode = w83627ehf_read_value(data, W83627EHF_REG_DIODE);
+ for (i = 0; i < 3; i++) {
+ if ((tmp & (0x02 << i)))
+ data->temp_type[i] = (diode & (0x10 << i)) ? 1 : 2;
+ else
+ data->temp_type[i] = 4; /* thermistor */
+ }
}
static int __devinit w83627ehf_probe(struct platform_device *pdev)
struct w83627ehf_sio_data *sio_data = dev->platform_data;
struct w83627ehf_data *data;
struct resource *res;
- u8 fan4pin, fan5pin;
+ u8 fan4pin, fan5pin, en_vrm10;
int i, err = 0;
res = platform_get_resource(pdev, IORESOURCE_IO, 0);
/* Initialize the chip */
w83627ehf_init_device(data);
- /* A few vars need to be filled upon startup */
- for (i = 0; i < 5; i++)
- data->fan_min[i] = w83627ehf_read_value(data,
- W83627EHF_REG_FAN_MIN[i]);
+ data->vrm = vid_which_vrm();
+ superio_enter(sio_data->sioreg);
+ /* Set VID input sensibility if needed. In theory the BIOS should
+ have set it, but in practice it's not always the case. */
+ en_vrm10 = superio_inb(sio_data->sioreg, SIO_REG_EN_VRM10);
+ if ((en_vrm10 & 0x08) && data->vrm != 100) {
+ dev_warn(dev, "Setting VID input voltage to TTL\n");
+ superio_outb(sio_data->sioreg, SIO_REG_EN_VRM10,
+ en_vrm10 & ~0x08);
+ } else if (!(en_vrm10 & 0x08) && data->vrm == 100) {
+ dev_warn(dev, "Setting VID input voltage to VRM10\n");
+ superio_outb(sio_data->sioreg, SIO_REG_EN_VRM10,
+ en_vrm10 | 0x08);
+ }
+ /* Read VID value */
+ superio_select(sio_data->sioreg, W83627EHF_LD_HWM);
+ if (superio_inb(sio_data->sioreg, SIO_REG_VID_CTRL) & 0x80)
+ data->vid = superio_inb(sio_data->sioreg, SIO_REG_VID_DATA) & 0x3f;
+ else {
+ dev_info(dev, "VID pins in output mode, CPU VID not "
+ "available\n");
+ data->vid = 0x3f;
+ }
/* fan4 and fan5 share some pins with the GPIO and serial flash */
- superio_enter(sio_data->sioreg);
fan5pin = superio_inb(sio_data->sioreg, 0x24) & 0x2;
fan4pin = superio_inb(sio_data->sioreg, 0x29) & 0x6;
superio_exit(sio_data->sioreg);
if (err)
goto exit_remove;
+ if (data->vid != 0x3f) {
+ err = device_create_file(dev, &dev_attr_cpu0_vid);
+ if (err)
+ goto exit_remove;
+ }
+
data->class_dev = hwmon_device_register(dev);
if (IS_ERR(data->class_dev)) {
err = PTR_ERR(data->class_dev);
sio_name = sio_name_W83627DHG;
break;
default:
- pr_info(DRVNAME ": unsupported chip ID: 0x%04x\n",
- val);
+ if (val != 0xffff)
+ pr_debug(DRVNAME ": unsupported chip ID: 0x%04x\n",
+ val);
superio_exit(sioaddr);
return -ENODEV;
}
| superio_inb(sioaddr, SIO_REG_ADDR + 1);
*addr = val & IOREGION_ALIGNMENT;
if (*addr == 0) {
+ printk(KERN_ERR DRVNAME ": Refusing to enable a Super-I/O "
+ "device with a base I/O port 0.\n");
superio_exit(sioaddr);
return -ENODEV;
}
/* Activate logical device if needed */
val = superio_inb(sioaddr, SIO_REG_ENABLE);
- if (!(val & 0x01))
+ if (!(val & 0x01)) {
+ printk(KERN_WARNING DRVNAME ": Forcibly enabling Super-I/O. "
+ "Sensor is probably unusable.\n");
superio_outb(sioaddr, SIO_REG_ENABLE, val | 0x01);
+ }
superio_exit(sioaddr);
pr_info(DRVNAME ": Found %s chip at %#x\n", sio_name, *addr);
projects / firefly-linux-kernel-4.4.55.git / blobdiff