Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6

[firefly-linux-kernel-4.4.55.git] / drivers / infiniband / hw / ipath / ipath_registers.h

diff --git a/drivers/infiniband/hw/ipath/ipath_registers.h b/drivers/infiniband/hw/ipath/ipath_registers.h
index 1e59750c5f63ddb30ab561700893582a2eed3529..6e23b3d632b820eac22febb91b0aab7d0269982a 100644 (file)
--- a/drivers/infiniband/hw/ipath/ipath_registers.h
+++ b/drivers/infiniband/hw/ipath/ipath_registers.h
@@ -1,4 +1,5 @@
 /*
+ * Copyright (c) 2006 QLogic, Inc. All rights reserved.
  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
  *
  * This software is available to you under a choice of one of two
@@ -34,8 +35,8 @@
 #define _IPATH_REGISTERS_H
 
 /*
- * This file should only be included by kernel source, and by the diags.
- * It defines the registers, and their contents, for the InfiniPath HT-400 chip
+ * This file should only be included by kernel source, and by the diags.  It
+ * defines the registers, and their contents, for InfiniPath chips.
  */
 
 /*
@@ -156,8 +157,10 @@
 #define INFINIPATH_IBCC_FLOWCTRLWATERMARK_SHIFT 8
 #define INFINIPATH_IBCC_LINKINITCMD_MASK 0x3ULL
 #define INFINIPATH_IBCC_LINKINITCMD_DISABLE 1
-#define INFINIPATH_IBCC_LINKINITCMD_POLL 2     /* cycle through TS1/TS2 till OK */
-#define INFINIPATH_IBCC_LINKINITCMD_SLEEP 3    /* wait for TS1, then go on */
+/* cycle through TS1/TS2 till OK */
+#define INFINIPATH_IBCC_LINKINITCMD_POLL 2
+/* wait for TS1, then go on */
+#define INFINIPATH_IBCC_LINKINITCMD_SLEEP 3
 #define INFINIPATH_IBCC_LINKINITCMD_SHIFT 16
 #define INFINIPATH_IBCC_LINKCMD_MASK 0x3ULL
 #define INFINIPATH_IBCC_LINKCMD_INIT 1 /* move to 0x11 */
@@ -182,7 +185,8 @@
 #define INFINIPATH_IBCS_LINKSTATE_SHIFT 4
 #define INFINIPATH_IBCS_TXREADY       0x40000000
 #define INFINIPATH_IBCS_TXCREDITOK    0x80000000
-/* link training states (shift by INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) */
+/* link training states (shift by
+   INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) */
 #define INFINIPATH_IBCS_LT_STATE_DISABLED      0x00
 #define INFINIPATH_IBCS_LT_STATE_LINKUP                0x01
 #define INFINIPATH_IBCS_LT_STATE_POLLACTIVE    0x02
@@ -267,19 +271,23 @@
 /* kr_serdesconfig0 bits */
 #define INFINIPATH_SERDC0_RESET_MASK  0xfULL   /* overal reset bits */
 #define INFINIPATH_SERDC0_RESET_PLL   0x10000000ULL    /* pll reset */
-#define INFINIPATH_SERDC0_TXIDLE      0xF000ULL        /* tx idle enables (per lane) */
-#define INFINIPATH_SERDC0_RXDETECT_EN 0xF0000ULL       /* rx detect enables (per lane) */
-#define INFINIPATH_SERDC0_L1PWR_DN      0xF0ULL        /* L1 Power down; use with RXDETECT,
-                                                          Otherwise not used on IB side */
+/* tx idle enables (per lane) */
+#define INFINIPATH_SERDC0_TXIDLE      0xF000ULL
+/* rx detect enables (per lane) */
+#define INFINIPATH_SERDC0_RXDETECT_EN 0xF0000ULL
+/* L1 Power down; use with RXDETECT, Otherwise not used on IB side */
+#define INFINIPATH_SERDC0_L1PWR_DN      0xF0ULL
 
 /* kr_xgxsconfig bits */
 #define INFINIPATH_XGXS_RESET          0x7ULL
 #define INFINIPATH_XGXS_MDIOADDR_MASK  0xfULL
 #define INFINIPATH_XGXS_MDIOADDR_SHIFT 4
+#define INFINIPATH_XGXS_RX_POL_SHIFT 19
+#define INFINIPATH_XGXS_RX_POL_MASK 0xfULL
 
 #define INFINIPATH_RT_ADDR_MASK 0xFFFFFFFFFFULL        /* 40 bits valid */
 
-/* TID entries (memory), HT400-only */
+/* TID entries (memory), HT-only */
 #define INFINIPATH_RT_VALID 0x8000000000000000ULL
 #define INFINIPATH_RT_ADDR_SHIFT 0
 #define INFINIPATH_RT_BUFSIZE_MASK 0x3FFF
@@ -390,12 +398,13 @@ struct ipath_kregs {
        ipath_kreg kr_txintmemsize;
        ipath_kreg kr_xgxsconfig;
        ipath_kreg kr_ibpllcfg;
-       /* use these two (and the following N ports) only with ipath_k*_kreg64_port();
-        * not *kreg64() */
+       /* use these two (and the following N ports) only with
+        * ipath_k*_kreg64_port(); not *kreg64() */
        ipath_kreg kr_rcvhdraddr;
        ipath_kreg kr_rcvhdrtailaddr;
 
-       /* remaining registers are not present on all types of infinipath chips  */
+       /* remaining registers are not present on all types of infinipath
+          chips  */
        ipath_kreg kr_rcvpktledcnt;
        ipath_kreg kr_pcierbuftestreg0;
        ipath_kreg kr_pcierbuftestreg1;