IB/qib: Use PCI Express Capability accessors

[firefly-linux-kernel-4.4.55.git] / drivers / infiniband / hw / qib / qib_pcie.c

diff --git a/drivers/infiniband/hw/qib/qib_pcie.c b/drivers/infiniband/hw/qib/qib_pcie.c
index 790646ef51060b4bda68f2a21f98a0a0421c8fd3..90013717321005e157f1920610f86b59efcb65f8 100644 (file)
--- a/drivers/infiniband/hw/qib/qib_pcie.c
+++ b/drivers/infiniband/hw/qib/qib_pcie.c
@@ -224,8 +224,9 @@ static void qib_msix_setup(struct qib_devdata *dd, int pos, u32 *msixcnt,
        }
 do_intx:
        if (ret) {
-               qib_dev_err(dd, "pci_enable_msix %d vectors failed: %d, "
-                           "falling back to INTx\n", tabsize, ret);
+               qib_dev_err(dd,
+                       "pci_enable_msix %d vectors failed: %d, falling back to INTx\n",
+                       tabsize, ret);
                tabsize = 0;
        }
        for (i = 0; i < tabsize; i++)
@@ -251,8 +252,9 @@ static int qib_msi_setup(struct qib_devdata *dd, int pos)
 
        ret = pci_enable_msi(pdev);
        if (ret)
-               qib_dev_err(dd, "pci_enable_msi failed: %d, "
-                           "interrupts may not work\n", ret);
+               qib_dev_err(dd,
+                       "pci_enable_msi failed: %d, interrupts may not work\n",
+                       ret);
        /* continue even if it fails, we may still be OK... */
 
        pci_read_config_dword(pdev, pos + PCI_MSI_ADDRESS_LO,
@@ -271,10 +273,9 @@ int qib_pcie_params(struct qib_devdata *dd, u32 minw, u32 *nent,
                    struct qib_msix_entry *entry)
 {
        u16 linkstat, speed;
-       int pos = 0, pose, ret = 1;
+       int pos = 0, ret = 1;
 
-       pose = pci_pcie_cap(dd->pcidev);
-       if (!pose) {
+       if (!pci_is_pcie(dd->pcidev)) {
                qib_dev_err(dd, "Can't find PCI Express capability!\n");
                /* set up something... */
                dd->lbus_width = 1;
@@ -296,7 +297,7 @@ int qib_pcie_params(struct qib_devdata *dd, u32 minw, u32 *nent,
        if (!pos)
                qib_enable_intx(dd->pcidev);
 
-       pci_read_config_word(dd->pcidev, pose + PCI_EXP_LNKSTA, &linkstat);
+       pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat);
        /*
         * speed is bits 0-3, linkwidth is bits 4-8
         * no defines for them in headers
@@ -358,8 +359,8 @@ int qib_reinit_intr(struct qib_devdata *dd)
 
        pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI);
        if (!pos) {
-               qib_dev_err(dd, "Can't find MSI capability, "
-                           "can't restore MSI settings\n");
+               qib_dev_err(dd,
+                       "Can't find MSI capability, can't restore MSI settings\n");
                ret = 0;
                /* nothing special for MSIx, just MSI */
                goto bail;
@@ -471,8 +472,8 @@ void qib_pcie_reenable(struct qib_devdata *dd, u16 cmd, u8 iline, u8 cline)
        pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, cline);
        r = pci_enable_device(dd->pcidev);
        if (r)
-               qib_dev_err(dd, "pci_enable_device failed after "
-                           "reset: %d\n", r);
+               qib_dev_err(dd,
+                       "pci_enable_device failed after reset: %d\n", r);
 }
 
 /* code to adjust PCIe capabilities. */
@@ -514,7 +515,6 @@ static int qib_tune_pcie_coalesce(struct qib_devdata *dd)
 {
        int r;
        struct pci_dev *parent;
-       int ppos;
        u16 devid;
        u32 mask, bits, val;
 
@@ -527,8 +527,7 @@ static int qib_tune_pcie_coalesce(struct qib_devdata *dd)
                qib_devinfo(dd->pcidev, "Parent not root\n");
                return 1;
        }
-       ppos = pci_pcie_cap(parent);
-       if (!ppos)
+       if (!pci_is_pcie(parent))
                return 1;
        if (parent->vendor != 0x8086)
                return 1;
@@ -585,7 +584,6 @@ static int qib_tune_pcie_caps(struct qib_devdata *dd)
 {
        int ret = 1; /* Assume the worst */
        struct pci_dev *parent;
-       int ppos, epos;
        u16 pcaps, pctl, ecaps, ectl;
        int rc_sup, ep_sup;
        int rc_cur, ep_cur;
@@ -596,19 +594,15 @@ static int qib_tune_pcie_caps(struct qib_devdata *dd)
                qib_devinfo(dd->pcidev, "Parent not root\n");
                goto bail;
        }
-       ppos = pci_pcie_cap(parent);
-       if (ppos) {
-               pci_read_config_word(parent, ppos + PCI_EXP_DEVCAP, &pcaps);
-               pci_read_config_word(parent, ppos + PCI_EXP_DEVCTL, &pctl);
-       } else
+
+       if (!pci_is_pcie(parent) || !pci_is_pcie(dd->pcidev))
                goto bail;
+       pcie_capability_read_word(parent, PCI_EXP_DEVCAP, &pcaps);
+       pcie_capability_read_word(parent, PCI_EXP_DEVCTL, &pctl);
        /* Find out supported and configured values for endpoint (us) */
-       epos = pci_pcie_cap(dd->pcidev);
-       if (epos) {
-               pci_read_config_word(dd->pcidev, epos + PCI_EXP_DEVCAP, &ecaps);
-               pci_read_config_word(dd->pcidev, epos + PCI_EXP_DEVCTL, &ectl);
-       } else
-               goto bail;
+       pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCAP, &ecaps);
+       pcie_capability_read_word(dd->pcidev, PCI_EXP_DEVCTL, &ectl);
+
        ret = 0;
        /* Find max payload supported by root, endpoint */
        rc_sup = fld2val(pcaps, PCI_EXP_DEVCAP_PAYLOAD);
@@ -627,14 +621,14 @@ static int qib_tune_pcie_caps(struct qib_devdata *dd)
                rc_cur = rc_sup;
                pctl = (pctl & ~PCI_EXP_DEVCTL_PAYLOAD) |
                        val2fld(rc_cur, PCI_EXP_DEVCTL_PAYLOAD);
-               pci_write_config_word(parent, ppos + PCI_EXP_DEVCTL, pctl);
+               pcie_capability_write_word(parent, PCI_EXP_DEVCTL, pctl);
        }
        /* If less than (allowed, supported), bump endpoint payload */
        if (rc_sup > ep_cur) {
                ep_cur = rc_sup;
                ectl = (ectl & ~PCI_EXP_DEVCTL_PAYLOAD) |
                        val2fld(ep_cur, PCI_EXP_DEVCTL_PAYLOAD);
-               pci_write_config_word(dd->pcidev, epos + PCI_EXP_DEVCTL, ectl);
+               pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL, ectl);
        }
 
        /*
@@ -652,13 +646,13 @@ static int qib_tune_pcie_caps(struct qib_devdata *dd)
                rc_cur = rc_sup;
                pctl = (pctl & ~PCI_EXP_DEVCTL_READRQ) |
                        val2fld(rc_cur, PCI_EXP_DEVCTL_READRQ);
-               pci_write_config_word(parent, ppos + PCI_EXP_DEVCTL, pctl);
+               pcie_capability_write_word(parent, PCI_EXP_DEVCTL, pctl);
        }
        if (rc_sup > ep_cur) {
                ep_cur = rc_sup;
                ectl = (ectl & ~PCI_EXP_DEVCTL_READRQ) |
                        val2fld(ep_cur, PCI_EXP_DEVCTL_READRQ);
-               pci_write_config_word(dd->pcidev, epos + PCI_EXP_DEVCTL, ectl);
+               pcie_capability_write_word(dd->pcidev, PCI_EXP_DEVCTL, ectl);
        }
 bail:
        return ret;
@@ -717,15 +711,16 @@ qib_pci_mmio_enabled(struct pci_dev *pdev)
                if (words == ~0ULL)
                        ret = PCI_ERS_RESULT_NEED_RESET;
        }
-       qib_devinfo(pdev, "QIB mmio_enabled function called, "
-                "read wordscntr %Lx, returning %d\n", words, ret);
+       qib_devinfo(pdev,
+               "QIB mmio_enabled function called, read wordscntr %Lx, returning %d\n",
+               words, ret);
        return  ret;
 }
 
 static pci_ers_result_t
 qib_pci_slot_reset(struct pci_dev *pdev)
 {
-       qib_devinfo(pdev, "QIB link_reset function called, ignored\n");
+       qib_devinfo(pdev, "QIB slot_reset function called, ignored\n");
        return PCI_ERS_RESULT_CAN_RECOVER;
 }