* System Control and Power Interface (SCPI) Message Protocol driver
*
* Copyright (C) 2014 ARM Ltd.
- * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
#include <linux/printk.h>
#include <linux/mailbox_client.h>
#include <linux/slab.h>
-#include <linux/rockchip/scpi.h>
-#include <linux/rockchip/rk3368-mailbox.h>
+#include <soc/rockchip/scpi.h>
+#include <soc/rockchip/rk3368-mailbox.h>
#define SCPI_VERSION 0x01000002 /* version: 1.0.0.2 */
SCPI_DDR_BANDWIDTH_GET,
SCPI_DDR_GET_FREQ,
SCPI_DDR_SEND_TIMING,
+ SCPI_DDR_DCLK_MODE,
};
enum scpi_sys_cmd {
}
EXPORT_SYMBOL_GPL(scpi_sys_set_jtagmux_on_off);
+int scpi_ddr_dclk_mode(u32 dclk_mode)
+{
+ struct scpi_data_buf sdata;
+ struct rk3368_mbox_msg mdata;
+ struct __packed1 {
+ u32 dclk_mode;
+ } tx_buf;
+ struct __packed2 {
+ u32 status;
+ } rx_buf;
+
+ tx_buf.dclk_mode = (u32)dclk_mode;
+ SCPI_SETUP_DBUF(sdata, mdata, SCPI_CL_DDR,
+ SCPI_DDR_DCLK_MODE, tx_buf, rx_buf);
+ return scpi_execute_cmd(&sdata);
+}
+EXPORT_SYMBOL_GPL(scpi_ddr_dclk_mode);
+
int scpi_ddr_init(u32 dram_speed_bin, u32 freq, u32 lcdc_type, u32 addr_mcu_el3)
{
struct scpi_data_buf sdata;
int scpi_ddr_set_clk_rate(u32 rate, u32 lcdc_type)
{
+ int ret;
+
struct scpi_data_buf sdata;
struct rk3368_mbox_msg mdata;
struct __packed1 {
} tx_buf;
struct __packed2 {
u32 status;
+ u32 freq;
} rx_buf;
tx_buf.clk_rate = (u32)rate;
tx_buf.lcdc_type = (u32)lcdc_type;
SCPI_SETUP_DBUF(sdata, mdata, SCPI_CL_DDR,
SCPI_DDR_SET_FREQ, tx_buf, rx_buf);
- return scpi_execute_cmd(&sdata);
+ ret = scpi_execute_cmd(&sdata);
+
+ if ((!ret) && (!rx_buf.status))
+ ret = rx_buf.freq;
+ else
+ ret = 0;
+
+ return ret;
}
EXPORT_SYMBOL_GPL(scpi_ddr_set_clk_rate);