int ret;
dbg_info("(%d)\n", mode);
- /* transport packet format */
- ret = lgdt3306a_set_reg_bit(state, 0x0071, 7, mode == LGDT3306A_MPEG_PARALLEL?1:0); /* TPSENB=0x80 */
+ /* transport packet format - TPSENB=0x80 */
+ ret = lgdt3306a_set_reg_bit(state, 0x0071, 7,
+ mode == LGDT3306A_MPEG_PARALLEL ? 1 : 0);
if (lg_chkerr(ret))
goto fail;
- /* start of packet signal duration */
- ret = lgdt3306a_set_reg_bit(state, 0x0071, 6, 0); /* TPSSOPBITEN=0x40; 0=byte duration, 1=bit duration */
+ /*
+ * start of packet signal duration
+ * TPSSOPBITEN=0x40; 0=byte duration, 1=bit duration
+ */
+ ret = lgdt3306a_set_reg_bit(state, 0x0071, 6, 0);
if (lg_chkerr(ret))
goto fail;
ret = lgdt3306a_read_reg(state, 0x0070, &val);
if (lg_chkerr(ret))
goto fail;
- val &= ~0xa8; /* Tristate bus; TPOUTEN=0x80, TPCLKOUTEN=0x20, TPDATAOUTEN=0x08 */
+ /*
+ * Tristate bus; TPOUTEN=0x80, TPCLKOUTEN=0x20,
+ * TPDATAOUTEN=0x08
+ */
+ val &= ~0xa8;
ret = lgdt3306a_write_reg(state, 0x0070, val);
if (lg_chkerr(ret))
goto fail;
- ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 1); /* AGCIFOUTENB=0x40; 1=Disable IFAGC pin */
+ /* AGCIFOUTENB=0x40; 1=Disable IFAGC pin */
+ ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 1);
if (lg_chkerr(ret))
goto fail;
} else {
- ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 0); /* enable IFAGC pin */
+ /* enable IFAGC pin */
+ ret = lgdt3306a_set_reg_bit(state, 0x0003, 6, 0);
if (lg_chkerr(ret))
goto fail;
dbg_info("(%d)\n", mode);
if (mode == 0) {
- ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0); /* into reset */
+ /* into reset */
+ ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 0);
if (lg_chkerr(ret))
goto fail;
- ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 0); /* power down */
+ /* power down */
+ ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 0);
if (lg_chkerr(ret))
goto fail;
} else {
- ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1); /* out of reset */
+ /* out of reset */
+ ret = lgdt3306a_set_reg_bit(state, 0x0000, 7, 1);
if (lg_chkerr(ret))
goto fail;
- ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 1); /* power up */
+ /* power up */
+ ret = lgdt3306a_set_reg_bit(state, 0x0000, 0, 1);
if (lg_chkerr(ret))
goto fail;
}
dbg_info("(%d)\n", enabled);
- /* 0=Manual 1=Auto(QAM only) */
- ret = lgdt3306a_set_reg_bit(state, 0x0002, 3, enabled);/* SPECINVAUTO=0x04 */
+ /* 0=Manual 1=Auto(QAM only) - SPECINVAUTO=0x04 */
+ ret = lgdt3306a_set_reg_bit(state, 0x0002, 3, enabled);
return ret;
}
dbg_info("(%d)\n", inversion);
#if 0
-/* FGR - spectral_inversion defaults already set for VSB and QAM; can enable later if desired */
+ /*
+ * FGR - spectral_inversion defaults already set for VSB and QAM;
+ * can enable later if desired
+ */
ret = lgdt3306a_set_inversion(state, inversion);
switch (p->modulation) {
case VSB_8:
- ret = lgdt3306a_set_inversion_auto(state, 0); /* Manual only for VSB */
+ /* Manual only for VSB */
+ ret = lgdt3306a_set_inversion_auto(state, 0);
break;
case QAM_64:
case QAM_256:
- ret = lgdt3306a_set_inversion_auto(state, 1); /* Auto ok for QAM */
+ /* Auto ok for QAM */
+ ret = lgdt3306a_set_inversion_auto(state, 1);
break;
default:
ret = -EINVAL;
switch (if_freq_khz) {
default:
- pr_warn("IF=%d KHz is not supportted, 3250 assumed\n", if_freq_khz);
+ pr_warn("IF=%d KHz is not supportted, 3250 assumed\n",
+ if_freq_khz);
/* fallthrough */
case 3250: /* 3.25Mhz */
nco1 = 0x34;
}
dbg_info("(%d)\n", enable);
- return lgdt3306a_set_reg_bit(state, 0x0002, 7, enable ? 0 : 1); /* NI2CRPTEN=0x80 */
+ /* NI2CRPTEN=0x80 */
+ return lgdt3306a_set_reg_bit(state, 0x0002, 7, enable ? 0 : 1);
}
static int lgdt3306a_sleep(struct lgdt3306a_state *state)
goto fail;
/* 4. Peak-to-peak voltage of ADC input signal */
- ret = lgdt3306a_set_reg_bit(state, 0x0004, 7, 1); /* ADCSEL1V=0x80=1Vpp; 0x00=2Vpp */
+
+ /* ADCSEL1V=0x80=1Vpp; 0x00=2Vpp */
+ ret = lgdt3306a_set_reg_bit(state, 0x0004, 7, 1);
if (lg_chkerr(ret))
goto fail;
/* 5. ADC output data capture clock phase */
- ret = lgdt3306a_set_reg_bit(state, 0x0004, 2, 0); /* 0=same phase as ADC clock */
+
+ /* 0=same phase as ADC clock */
+ ret = lgdt3306a_set_reg_bit(state, 0x0004, 2, 0);
if (lg_chkerr(ret))
goto fail;
/* 5a. ADC sampling clock source */
- ret = lgdt3306a_set_reg_bit(state, 0x0004, 3, 0); /* ADCCLKPLLSEL=0x08; 0=use ext clock, not PLL */
+
+ /* ADCCLKPLLSEL=0x08; 0=use ext clock, not PLL */
+ ret = lgdt3306a_set_reg_bit(state, 0x0004, 3, 0);
if (lg_chkerr(ret))
goto fail;
/* 6. Automatic PLL set */
- ret = lgdt3306a_set_reg_bit(state, 0x0005, 6, 0); /* PLLSETAUTO=0x40; 0=off */
+
+ /* PLLSETAUTO=0x40; 0=off */
+ ret = lgdt3306a_set_reg_bit(state, 0x0005, 6, 0);
if (lg_chkerr(ret))
goto fail;
goto fail;
ret = lgdt3306a_spectral_inversion(state, p,
- state->cfg->spectral_inversion ? 1 : 0);
+ state->cfg->spectral_inversion ? 1 : 0);
if (lg_chkerr(ret))
goto fail;
struct lgdt3306a_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
- dbg_info("(%u, %d)\n", state->current_frequency, state->current_modulation);
+ dbg_info("(%u, %d)\n",
+ state->current_frequency, state->current_modulation);
p->modulation = state->current_modulation;
p->frequency = state->current_frequency;
if (ret)
return ret;
val &= 0xf8;
- if ((snrRef > 18) && (maxPowerMan > 0x68) && (nCombDet == 0x01) && ((fbDlyCir == 0x03FF) || (fbDlyCir < 0x6C))) {
+ if ((snrRef > 18) && (maxPowerMan > 0x68)
+ && (nCombDet == 0x01)
+ && ((fbDlyCir == 0x03FF) || (fbDlyCir < 0x6C))) {
/* SNR is over 18dB and no ghosting */
val |= 0x00; /* final bandwidth = 0 */
} else {
return ret;
}
-static enum lgdt3306a_modulation lgdt3306a_check_oper_mode(struct lgdt3306a_state *state)
+static enum lgdt3306a_modulation
+lgdt3306a_check_oper_mode(struct lgdt3306a_state *state)
{
u8 val = 0;
int ret;
if (val & 0x01) {
dbg_info("QAM256\n");
return LG3306_QAM256;
- } else {
- dbg_info("QAM64\n");
- return LG3306_QAM64;
}
+ dbg_info("QAM64\n");
+ return LG3306_QAM64;
}
err:
pr_warn("UNKNOWN\n");
return LG3306_UNKNOWN_MODE;
}
-static enum lgdt3306a_lock_status lgdt3306a_check_lock_status(struct lgdt3306a_state *state,
- enum lgdt3306a_lock_check whatLock)
+static enum lgdt3306a_lock_status
+lgdt3306a_check_lock_status(struct lgdt3306a_state *state,
+ enum lgdt3306a_lock_check whatLock)
{
u8 val = 0;
int ret;
return lockStatus;
}
-static enum lgdt3306a_neverlock_status lgdt3306a_check_neverlock_status(struct lgdt3306a_state *state)
+static enum lgdt3306a_neverlock_status
+lgdt3306a_check_neverlock_status(struct lgdt3306a_state *state)
{
u8 val = 0;
int ret;
snrRef, mainStrong, aiccrejStatus, currChDiffACQ);
#if 0
- if ((mainStrong == 0) && (currChDiffACQ > 0x70)) /* Dynamic ghost exists */
+ /* Dynamic ghost exists */
+ if ((mainStrong == 0) && (currChDiffACQ > 0x70))
#endif
if (mainStrong == 0) {
ret = lgdt3306a_read_reg(state, 0x2135, &val);
return 0;
}
-static enum lgdt3306a_lock_status lgdt3306a_sync_lock_poll(struct lgdt3306a_state *state)
+static enum lgdt3306a_lock_status
+lgdt3306a_sync_lock_poll(struct lgdt3306a_state *state)
{
enum lgdt3306a_lock_status syncLockStatus = LG3306_UNLOCK;
int i;
for (i = 0; i < 2; i++) {
msleep(30);
- syncLockStatus = lgdt3306a_check_lock_status(state, LG3306_SYNC_LOCK);
+ syncLockStatus = lgdt3306a_check_lock_status(state,
+ LG3306_SYNC_LOCK);
if (syncLockStatus == LG3306_LOCK) {
dbg_info("locked(%d)\n", i);
return LG3306_UNLOCK;
}
-static enum lgdt3306a_lock_status lgdt3306a_fec_lock_poll(struct lgdt3306a_state *state)
+static enum lgdt3306a_lock_status
+lgdt3306a_fec_lock_poll(struct lgdt3306a_state *state)
{
enum lgdt3306a_lock_status FECLockStatus = LG3306_UNLOCK;
int i;
for (i = 0; i < 2; i++) {
msleep(30);
- FECLockStatus = lgdt3306a_check_lock_status(state, LG3306_FEC_LOCK);
+ FECLockStatus = lgdt3306a_check_lock_status(state,
+ LG3306_FEC_LOCK);
if (FECLockStatus == LG3306_LOCK) {
dbg_info("locked(%d)\n", i);
return FECLockStatus;
}
-static enum lgdt3306a_neverlock_status lgdt3306a_neverlock_poll(struct lgdt3306a_state *state)
+static enum lgdt3306a_neverlock_status
+lgdt3306a_neverlock_poll(struct lgdt3306a_state *state)
{
enum lgdt3306a_neverlock_status NLLockStatus = LG3306_NL_FAIL;
int i;
return val;
}
+static const u32 valx_x10[] = {
+ 10, 11, 13, 15, 17, 20, 25, 33, 41, 50, 59, 73, 87, 100
+};
+static const u32 log10x_x1000[] = {
+ 0, 41, 114, 176, 230, 301, 398, 518, 613, 699, 771, 863, 939, 1000
+};
+
static u32 log10_x1000(u32 x)
{
- static u32 valx_x10[] = { 10, 11, 13, 15, 17, 20, 25, 33, 41, 50, 59, 73, 87, 100 };
- static u32 log10x_x1000[] = { 0, 41, 114, 176, 230, 301, 398, 518, 613, 699, 771, 863, 939, 1000 };
- static u32 nelems = sizeof(valx_x10)/sizeof(valx_x10[0]);
u32 diff_val, step_val, step_log10;
u32 log_val = 0;
u32 i;
if (x <= 0)
return -1000000; /* signal error */
+ if (x == 10)
+ return 0; /* log(1)=0 */
+
if (x < 10) {
while (x < 10) {
x = x * 10;
log_val--;
}
- } else if (x == 10) {
- return 0; /* log(1)=0 */
- } else {
+ } else { /* x > 10 */
while (x >= 100) {
x = x / 10;
log_val++;
return log_val; /* don't need to interpolate */
/* find our place on the log curve */
- for (i = 1; i < nelems; i++) {
+ for (i = 1; i < ARRAY_SIZE(valx_x10); i++) {
if (valx_x10[i] >= x)
break;
}
- if (i == nelems)
+ if (i == ARRAY_SIZE(valx_x10))
return log_val + log10x_x1000[i - 1];
diff_val = x - valx_x10[i-1];
return snr_x100;
}
-static enum lgdt3306a_lock_status lgdt3306a_vsb_lock_poll(struct lgdt3306a_state *state)
+static enum lgdt3306a_lock_status
+lgdt3306a_vsb_lock_poll(struct lgdt3306a_state *state)
{
int ret;
u8 cnt = 0;
u8 packet_error;
u32 snr;
- while (1) {
+ for (cnt = 0; cnt < 10; cnt++) {
if (lgdt3306a_sync_lock_poll(state) == LG3306_UNLOCK) {
dbg_info("no sync lock!\n");
return LG3306_UNLOCK;
- } else {
- msleep(20);
- ret = lgdt3306a_pre_monitoring(state);
- if (ret)
- return LG3306_UNLOCK;
+ }
- packet_error = lgdt3306a_get_packet_error(state);
- snr = lgdt3306a_calculate_snr_x100(state);
- dbg_info("cnt=%d errors=%d snr=%d\n",
- cnt, packet_error, snr);
+ msleep(20);
+ ret = lgdt3306a_pre_monitoring(state);
+ if (ret)
+ break;
- if ((snr < 1500) || (packet_error >= 0xff))
- cnt++;
- else
- return LG3306_LOCK;
+ packet_error = lgdt3306a_get_packet_error(state);
+ snr = lgdt3306a_calculate_snr_x100(state);
+ dbg_info("cnt=%d errors=%d snr=%d\n", cnt, packet_error, snr);
- if (cnt >= 10) {
- dbg_info("not locked!\n");
- return LG3306_UNLOCK;
- }
- }
+ if ((snr >= 1500) && (packet_error < 0xff))
+ return LG3306_LOCK;
}
+
+ dbg_info("not locked!\n");
return LG3306_UNLOCK;
}
-static enum lgdt3306a_lock_status lgdt3306a_qam_lock_poll(struct lgdt3306a_state *state)
+static enum lgdt3306a_lock_status
+lgdt3306a_qam_lock_poll(struct lgdt3306a_state *state)
{
- u8 cnt = 0;
+ u8 cnt;
u8 packet_error;
u32 snr;
- while (1) {
+ for (cnt = 0; cnt < 10; cnt++) {
if (lgdt3306a_fec_lock_poll(state) == LG3306_UNLOCK) {
dbg_info("no fec lock!\n");
return LG3306_UNLOCK;
- } else {
- msleep(20);
+ }
- packet_error = lgdt3306a_get_packet_error(state);
- snr = lgdt3306a_calculate_snr_x100(state);
- dbg_info("cnt=%d errors=%d snr=%d\n",
- cnt, packet_error, snr);
+ msleep(20);
- if ((snr < 1500) || (packet_error >= 0xff))
- cnt++;
- else
- return LG3306_LOCK;
+ packet_error = lgdt3306a_get_packet_error(state);
+ snr = lgdt3306a_calculate_snr_x100(state);
+ dbg_info("cnt=%d errors=%d snr=%d\n", cnt, packet_error, snr);
- if (cnt >= 10) {
- dbg_info("not locked!\n");
- return LG3306_UNLOCK;
- }
- }
+ if ((snr >= 1500) && (packet_error < 0xff))
+ return LG3306_LOCK;
}
+
+ dbg_info("not locked!\n");
return LG3306_UNLOCK;
}
if (fe->ops.tuner_ops.get_rf_strength) {
ret = fe->ops.tuner_ops.get_rf_strength(fe, &strength);
- if (ret == 0) {
+ if (ret == 0)
dbg_info("strength=%d\n", strength);
- } else {
+ else
dbg_info("fe->ops.tuner_ops.get_rf_strength() failed\n");
- }
}
*status = 0;
*ber = 0;
#if 1
- /* FGR - BUGBUG - I don't know what value is expected by dvb_core
+ /* FGR - FIXME - I don't know what value is expected by dvb_core
* what is the scale of the value?? */
tmp = read_reg(state, 0x00fc); /* NBERVALUE[24-31] */
tmp = (tmp << 8) | read_reg(state, 0x00fd); /* NBERVALUE[16-23] */
*ucblocks = 0;
#if 1
- /* FGR - BUGBUG - I don't know what value is expected by dvb_core
+ /* FGR - FIXME - I don't know what value is expected by dvb_core
* what happens when value wraps? */
*ucblocks = read_reg(state, 0x00f4); /* TPIFTPERRCNT[0-7] */
dbg_info("ucblocks=%u\n", *ucblocks);
return 0;
}
-static int lgdt3306a_tune(struct dvb_frontend *fe, bool re_tune, unsigned int mode_flags, unsigned int *delay, fe_status_t *status)
+static int lgdt3306a_tune(struct dvb_frontend *fe, bool re_tune,
+ unsigned int mode_flags, unsigned int *delay,
+ fe_status_t *status)
{
int ret = 0;
struct lgdt3306a_state *state = fe->demodulator_priv;
if ((val & 0x74) != 0x74) {
pr_warn("expected 0x74, got 0x%x\n", (val & 0x74));
#if 0
- goto fail; /* BUGBUG - re-enable when we know this is right */
+ /* FIXME - re-enable when we know this is right */
+ goto fail;
#endif
}
ret = lgdt3306a_read_reg(state, 0x0001, &val);
if ((val & 0xf6) != 0xc6) {
pr_warn("expected 0xc6, got 0x%x\n", (val & 0xf6));
#if 0
- goto fail; /* BUGBUG - re-enable when we know this is right */
+ /* FIXME - re-enable when we know this is right */
+ goto fail;
#endif
}
ret = lgdt3306a_read_reg(state, 0x0002, &val);
if ((val & 0x73) != 0x03) {
pr_warn("expected 0x03, got 0x%x\n", (val & 0x73));
#if 0
- goto fail; /* BUGBUG - re-enable when we know this is right */
+ /* FIXME - re-enable when we know this is right */
+ goto fail;
#endif
}
projects / firefly-linux-kernel-4.4.55.git / blobdiff