struct spear_pcie_gadget_config *config,
const char *buf, size_t count)
{
- if (strict_strtoul(buf, 0, &config->requested_msi))
- return -EINVAL;
+ int ret;
+
+ ret = kstrtoul(buf, 0, &config->requested_msi);
+ if (ret)
+ return ret;
+
if (config->requested_msi > 32)
config->requested_msi = 32;
{
struct pcie_app_reg __iomem *app_reg = config->va_app_base;
ulong en;
+ int ret;
- if (strict_strtoul(buf, 0, &en))
- return -EINVAL;
+ ret = kstrtoul(buf, 0, &en);
+ if (ret)
+ return ret;
if (en)
writel(readl(&app_reg->app_ctrl_0) | (1 << SYS_INT_ID),
struct pcie_app_reg __iomem *app_reg = config->va_app_base;
ulong vector;
u32 ven_msi;
+ int ret;
- if (strict_strtoul(buf, 0, &vector))
- return -EINVAL;
+ ret = kstrtoul(buf, 0, &vector);
+ if (ret)
+ return ret;
if (!config->configured_msi)
return -EINVAL;
const char *buf, size_t count)
{
ulong id;
+ int ret;
- if (strict_strtoul(buf, 0, &id))
- return -EINVAL;
+ ret = kstrtoul(buf, 0, &id);
+ if (ret)
+ return ret;
spear_dbi_write_reg(config, PCI_VENDOR_ID, 2, id);
const char *buf, size_t count)
{
ulong id;
+ int ret;
- if (strict_strtoul(buf, 0, &id))
- return -EINVAL;
+ ret = kstrtoul(buf, 0, &id);
+ if (ret)
+ return ret;
spear_dbi_write_reg(config, PCI_DEVICE_ID, 2, id);
ulong size;
u32 pos, pos1;
u32 no_of_bit = 0;
+ int ret;
+
+ ret = kstrtoul(buf, 0, &size);
+ if (ret)
+ return ret;
- if (strict_strtoul(buf, 0, &size))
- return -EINVAL;
/* min bar size is 256 */
if (size <= 0x100)
size = 0x100;
{
struct pcie_app_reg __iomem *app_reg = config->va_app_base;
ulong address;
+ int ret;
- if (strict_strtoul(buf, 0, &address))
- return -EINVAL;
+ ret = kstrtoul(buf, 0, &address);
+ if (ret)
+ return ret;
address &= ~(config->bar0_size - 1);
if (config->va_bar0_address)
const char *buf, size_t count)
{
ulong offset;
+ int ret;
- if (strict_strtoul(buf, 0, &offset))
- return -EINVAL;
+ ret = kstrtoul(buf, 0, &offset);
+ if (ret)
+ return ret;
if (offset % 4)
return -EINVAL;
const char *buf, size_t count)
{
ulong data;
+ int ret;
- if (strict_strtoul(buf, 0, &data))
- return -EINVAL;
+ ret = kstrtoul(buf, 0, &data);
+ if (ret)
+ return ret;
if (!config->va_bar0_address)
return -ENOMEM;
goto err_iounmap_app;
}
- dev_set_drvdata(&pdev->dev, target);
+ platform_set_drvdata(pdev, target);
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
clk = clk_get_sys("pcie1", NULL);
if (IS_ERR(clk)) {
pr_err("%s:couldn't get clk for pcie1\n", __func__);
+ status = PTR_ERR(clk);
goto err_irq;
}
- if (clk_enable(clk)) {
+ status = clk_enable(clk);
+ if (status) {
pr_err("%s:couldn't enable clk for pcie1\n", __func__);
goto err_irq;
}
clk = clk_get_sys("pcie2", NULL);
if (IS_ERR(clk)) {
pr_err("%s:couldn't get clk for pcie2\n", __func__);
+ status = PTR_ERR(clk);
goto err_irq;
}
- if (clk_enable(clk)) {
+ status = clk_enable(clk);
+ if (status) {
pr_err("%s:couldn't enable clk for pcie2\n", __func__);
goto err_irq;
}
res0 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
res1 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
irq = platform_get_irq(pdev, 0);
- target = dev_get_drvdata(&pdev->dev);
+ target = platform_get_drvdata(pdev);
config = &target->config;
free_irq(irq, NULL);