mtd: eLBC NAND: increase bus timeout to maximum

[firefly-linux-kernel-4.4.55.git] / drivers / mtd / nand / fsl_elbc_nand.c

diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index 1f6eb2578717e479904efad7387164e18d702547..58db2785512697b2478067aee2cf2ef9978cb4b7 100644 (file)
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -739,7 +739,8 @@ static int fsl_elbc_chip_init_tail(struct mtd_info *mtd)
 
 static int fsl_elbc_read_page(struct mtd_info *mtd,
                               struct nand_chip *chip,
-                              uint8_t *buf)
+                             uint8_t *buf,
+                             int page)
 {
        fsl_elbc_read_buf(mtd, buf, mtd->writesize);
        fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
@@ -945,6 +946,13 @@ static int __devinit fsl_elbc_ctrl_init(struct fsl_elbc_ctrl *ctrl)
 {
        struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 
+       /*
+        * NAND transactions can tie up the bus for a long time, so set the
+        * bus timeout to max by clearing LBCR[BMT] (highest base counter
+        * value) and setting LBCR[BMTPS] to the highest prescaler value.
+        */
+       clrsetbits_be32(&lbc->lbcr, LBCR_BMT, 15);
+
        /* clear event registers */
        setbits32(&lbc->ltesr, LTESR_NAND_MASK);
        out_be32(&lbc->lteatr, 0);