mtd: spi-nor: s25fl204k supports dual I/0

[firefly-linux-kernel-4.4.55.git] / drivers / mtd / spi-nor / spi-nor.c

diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
index f59aedfe1462a431018de993543c4abc69131eed..87d66a1ec1015c30b8bfce2dd14b39e9570e63b0 100644 (file)
--- a/drivers/mtd/spi-nor/spi-nor.c
+++ b/drivers/mtd/spi-nor/spi-nor.c
@@ -16,6 +16,7 @@
 #include <linux/device.h>
 #include <linux/mutex.h>
 #include <linux/math64.h>
+#include <linux/sizes.h>
 
 #include <linux/mtd/cfi.h>
 #include <linux/mtd/mtd.h>
@@ -24,7 +25,18 @@
 #include <linux/mtd/spi-nor.h>
 
 /* Define max times to check status register before we give up. */
-#define        MAX_READY_WAIT_JIFFIES  (40 * HZ) /* M25P16 specs 40s max chip erase */
+
+/*
+ * For everything but full-chip erase; probably could be much smaller, but kept
+ * around for safety for now
+ */
+#define DEFAULT_READY_WAIT_JIFFIES             (40UL * HZ)
+
+/*
+ * For full-chip erase, calibrated to a 2MB flash (M25P16); should be scaled up
+ * for larger flash
+ */
+#define CHIP_ERASE_2MB_READY_WAIT_JIFFIES      (40UL * HZ)
 
 #define SPI_NOR_MAX_ID_LEN     6
 
@@ -145,7 +157,7 @@ static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor)
 static inline int write_sr(struct spi_nor *nor, u8 val)
 {
        nor->cmd_buf[0] = val;
-       return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0);
+       return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1);
 }
 
 /*
@@ -154,7 +166,7 @@ static inline int write_sr(struct spi_nor *nor, u8 val)
  */
 static inline int write_enable(struct spi_nor *nor)
 {
-       return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0);
+       return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0);
 }
 
 /*
@@ -162,7 +174,7 @@ static inline int write_enable(struct spi_nor *nor)
  */
 static inline int write_disable(struct spi_nor *nor)
 {
-       return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0, 0);
+       return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0);
 }
 
 static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
@@ -188,7 +200,7 @@ static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
                        write_enable(nor);
 
                cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
-               status = nor->write_reg(nor, cmd, NULL, 0, 0);
+               status = nor->write_reg(nor, cmd, NULL, 0);
                if (need_wren)
                        write_disable(nor);
 
@@ -196,7 +208,7 @@ static inline int set_4byte(struct spi_nor *nor, const struct flash_info *info,
        default:
                /* Spansion style */
                nor->cmd_buf[0] = enable << 7;
-               return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1, 0);
+               return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1);
        }
 }
 static inline int spi_nor_sr_ready(struct spi_nor *nor)
@@ -233,12 +245,13 @@ static int spi_nor_ready(struct spi_nor *nor)
  * Service routine to read status register until ready, or timeout occurs.
  * Returns non-zero if error.
  */
-static int spi_nor_wait_till_ready(struct spi_nor *nor)
+static int spi_nor_wait_till_ready_with_timeout(struct spi_nor *nor,
+                                               unsigned long timeout_jiffies)
 {
        unsigned long deadline;
        int timeout = 0, ret;
 
-       deadline = jiffies + MAX_READY_WAIT_JIFFIES;
+       deadline = jiffies + timeout_jiffies;
 
        while (!timeout) {
                if (time_after_eq(jiffies, deadline))
@@ -258,6 +271,12 @@ static int spi_nor_wait_till_ready(struct spi_nor *nor)
        return -ETIMEDOUT;
 }
 
+static int spi_nor_wait_till_ready(struct spi_nor *nor)
+{
+       return spi_nor_wait_till_ready_with_timeout(nor,
+                                                   DEFAULT_READY_WAIT_JIFFIES);
+}
+
 /*
  * Erase the whole flash memory
  *
@@ -265,9 +284,9 @@ static int spi_nor_wait_till_ready(struct spi_nor *nor)
  */
 static int erase_chip(struct spi_nor *nor)
 {
-       dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd->size >> 10));
+       dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd.size >> 10));
 
-       return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0, 0);
+       return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0);
 }
 
 static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops)
@@ -321,6 +340,8 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
 
        /* whole-chip erase? */
        if (len == mtd->size) {
+               unsigned long timeout;
+
                write_enable(nor);
 
                if (erase_chip(nor)) {
@@ -328,7 +349,16 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
                        goto erase_err;
                }
 
-               ret = spi_nor_wait_till_ready(nor);
+               /*
+                * Scale the timeout linearly with the size of the flash, with
+                * a minimum calibrated to an old 2MB flash. We could try to
+                * pull these from CFI/SFDP, but these values should be good
+                * enough for now.
+                */
+               timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
+                             CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
+                             (unsigned long)(mtd->size / SZ_2M));
+               ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
                if (ret)
                        goto erase_err;
 
@@ -373,7 +403,7 @@ erase_err:
 
 static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
 {
-       struct mtd_info *mtd = nor->mtd;
+       struct mtd_info *mtd = &nor->mtd;
        uint32_t offset = ofs;
        uint8_t status_old, status_new;
        int ret = 0;
@@ -407,7 +437,7 @@ static int stm_lock(struct spi_nor *nor, loff_t ofs, uint64_t len)
 
 static int stm_unlock(struct spi_nor *nor, loff_t ofs, uint64_t len)
 {
-       struct mtd_info *mtd = nor->mtd;
+       struct mtd_info *mtd = &nor->mtd;
        uint32_t offset = ofs;
        uint8_t status_old, status_new;
        int ret = 0;
@@ -585,6 +615,7 @@ static const struct flash_info spi_nor_ids[] = {
 
        /* Micron */
        { "n25q032",     INFO(0x20ba16, 0, 64 * 1024,   64, SPI_NOR_QUAD_READ) },
+       { "n25q032a",    INFO(0x20bb16, 0, 64 * 1024,   64, SPI_NOR_QUAD_READ) },
        { "n25q064",     INFO(0x20ba17, 0, 64 * 1024,  128, SECT_4K | SPI_NOR_QUAD_READ) },
        { "n25q064a",    INFO(0x20bb17, 0, 64 * 1024,  128, SECT_4K | SPI_NOR_QUAD_READ) },
        { "n25q128a11",  INFO(0x20bb18, 0, 64 * 1024,  256, SPI_NOR_QUAD_READ) },
@@ -618,12 +649,12 @@ static const struct flash_info spi_nor_ids[] = {
        { "s25sl016a",  INFO(0x010214,      0,  64 * 1024,  32, 0) },
        { "s25sl032a",  INFO(0x010215,      0,  64 * 1024,  64, 0) },
        { "s25sl064a",  INFO(0x010216,      0,  64 * 1024, 128, 0) },
-       { "s25fl008k",  INFO(0xef4014,      0,  64 * 1024,  16, SECT_4K) },
-       { "s25fl016k",  INFO(0xef4015,      0,  64 * 1024,  32, SECT_4K) },
+       { "s25fl008k",  INFO(0xef4014,      0,  64 * 1024,  16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+       { "s25fl016k",  INFO(0xef4015,      0,  64 * 1024,  32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
        { "s25fl064k",  INFO(0xef4017,      0,  64 * 1024, 128, SECT_4K) },
        { "s25fl132k",  INFO(0x014016,      0,  64 * 1024,  64, SECT_4K) },
        { "s25fl164k",  INFO(0x014017,      0,  64 * 1024, 128, SECT_4K) },
-       { "s25fl204k",  INFO(0x014013,      0,  64 * 1024,   8, SECT_4K) },
+       { "s25fl204k",  INFO(0x014013,      0,  64 * 1024,   8, SECT_4K | SPI_NOR_DUAL_READ) },
 
        /* SST -- large erase sizes are "overlays", "sectors" are 4K */
        { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024,  8, SECT_4K | SST_WRITE) },
@@ -635,6 +666,7 @@ static const struct flash_info spi_nor_ids[] = {
        { "sst25wf010",  INFO(0xbf2502, 0, 64 * 1024,  2, SECT_4K | SST_WRITE) },
        { "sst25wf020",  INFO(0xbf2503, 0, 64 * 1024,  4, SECT_4K | SST_WRITE) },
        { "sst25wf020a", INFO(0x621612, 0, 64 * 1024,  4, SECT_4K) },
+       { "sst25wf040b", INFO(0x621613, 0, 64 * 1024,  8, SECT_4K) },
        { "sst25wf040",  INFO(0xbf2504, 0, 64 * 1024,  8, SECT_4K | SST_WRITE) },
        { "sst25wf080",  INFO(0xbf2505, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
 
@@ -687,6 +719,7 @@ static const struct flash_info spi_nor_ids[] = {
        { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
        { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
        { "w25q64dw", INFO(0xef6017, 0, 64 * 1024, 128, SECT_4K) },
+       { "w25q128fw", INFO(0xef6018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
        { "w25q80", INFO(0xef5014, 0, 64 * 1024,  16, SECT_4K) },
        { "w25q80bl", INFO(0xef4014, 0, 64 * 1024,  16, SECT_4K) },
        { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
@@ -868,8 +901,7 @@ static int macronix_quad_enable(struct spi_nor *nor)
        val = read_sr(nor);
        write_enable(nor);
 
-       nor->cmd_buf[0] = val | SR_QUAD_EN_MX;
-       nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0);
+       write_sr(nor, val | SR_QUAD_EN_MX);
 
        if (spi_nor_wait_till_ready(nor))
                return 1;
@@ -894,7 +926,7 @@ static int write_sr_cr(struct spi_nor *nor, u16 val)
        nor->cmd_buf[0] = val & 0xff;
        nor->cmd_buf[1] = (val >> 8);
 
-       return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2, 0);
+       return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2);
 }
 
 static int spansion_quad_enable(struct spi_nor *nor)
@@ -936,7 +968,7 @@ static int micron_quad_enable(struct spi_nor *nor)
 
        /* set EVCR, enable quad I/O */
        nor->cmd_buf[0] = val & ~EVCR_QUAD_EN_MICRON;
-       ret = nor->write_reg(nor, SPINOR_OP_WD_EVCR, nor->cmd_buf, 1, 0);
+       ret = nor->write_reg(nor, SPINOR_OP_WD_EVCR, nor->cmd_buf, 1);
        if (ret < 0) {
                dev_err(nor->dev, "error while writing EVCR register\n");
                return ret;
@@ -1004,8 +1036,8 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
 {
        const struct flash_info *info = NULL;
        struct device *dev = nor->dev;
-       struct mtd_info *mtd = nor->mtd;
-       struct device_node *np = dev->of_node;
+       struct mtd_info *mtd = &nor->mtd;
+       struct device_node *np = nor->flash_node;
        int ret;
        int i;
 
@@ -1061,6 +1093,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, enum read_mode mode)
 
        if (!mtd->name)
                mtd->name = dev_name(dev);
+       mtd->priv = nor;
        mtd->type = MTD_NORFLASH;
        mtd->writesize = 1;
        mtd->flags = MTD_CAP_NORFLASH;