Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net

[firefly-linux-kernel-4.4.55.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_sp.c

diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c
index 66ab259080867cf627dc3451f699860c709975c3..32a9609cc98bcd36e56b0193bba3a3508424f5cb 100644 (file)
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c
@@ -4432,6 +4432,8 @@ static void bnx2x_q_fill_init_tx_data(struct bnx2x_queue_sp_obj *o,
        tx_data->force_default_pri_flg =
                test_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, flags);
 
+       tx_data->tunnel_lso_inc_ip_id =
+               test_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, flags);
        tx_data->tunnel_non_lso_pcsum_location =
                test_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, flags) ? PCSUM_ON_PKT :
                                                                  PCSUM_ON_BD;
@@ -5679,17 +5681,18 @@ static inline int bnx2x_func_send_start(struct bnx2x *bp,
        memset(rdata, 0, sizeof(*rdata));
 
        /* Fill the ramrod data with provided parameters */
-       rdata->function_mode    = (u8)start_params->mf_mode;
-       rdata->sd_vlan_tag      = cpu_to_le16(start_params->sd_vlan_tag);
-       rdata->path_id          = BP_PATH(bp);
-       rdata->network_cos_mode = start_params->network_cos_mode;
-
-       /*
-        *  No need for an explicit memory barrier here as long we would
-        *  need to ensure the ordering of writing to the SPQ element
-        *  and updating of the SPQ producer which involves a memory
-        *  read and we will have to put a full memory barrier there
-        *  (inside bnx2x_sp_post()).
+       rdata->function_mode    = (u8)start_params->mf_mode;
+       rdata->sd_vlan_tag      = cpu_to_le16(start_params->sd_vlan_tag);
+       rdata->path_id          = BP_PATH(bp);
+       rdata->network_cos_mode = start_params->network_cos_mode;
+       rdata->gre_tunnel_mode  = start_params->gre_tunnel_mode;
+       rdata->gre_tunnel_rss   = start_params->gre_tunnel_rss;
+
+       /* No need for an explicit memory barrier here as long we would
+        * need to ensure the ordering of writing to the SPQ element
+        * and updating of the SPQ producer which involves a memory
+        * read and we will have to put a full memory barrier there
+        * (inside bnx2x_sp_post()).
         */
 
        return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_FUNCTION_START, 0,