Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net

[firefly-linux-kernel-4.4.55.git] / drivers / net / ethernet / broadcom / tg3.h

diff --git a/drivers/net/ethernet/broadcom/tg3.h b/drivers/net/ethernet/broadcom/tg3.h
index eb41b6f517a16a2afad82bf4bca052632ac3b351..9b2d3ac2474adda8e25398460f33d0abca38b05a 100644 (file)
--- a/drivers/net/ethernet/broadcom/tg3.h
+++ b/drivers/net/ethernet/broadcom/tg3.h
@@ -2198,6 +2198,8 @@
 
 #define NIC_SRAM_DATA_CFG_3            0x00000d3c
 #define  NIC_SRAM_ASPM_DEBOUNCE                 0x00000002
+#define  NIC_SRAM_LNK_FLAP_AVOID        0x00400000
+#define  NIC_SRAM_1G_ON_VAUX_OK                 0x00800000
 
 #define NIC_SRAM_DATA_CFG_4            0x00000d60
 #define  NIC_SRAM_GMII_MODE             0x00000002
@@ -2222,6 +2224,12 @@
 #define  NIC_SRAM_MBUF_POOL_BASE5705   0x00010000
 #define  NIC_SRAM_MBUF_POOL_SIZE5705   0x0000e000
 
+#define TG3_SRAM_RXCPU_SCRATCH_BASE_57766      0x00030000
+#define  TG3_SRAM_RXCPU_SCRATCH_SIZE_57766      0x00010000
+#define TG3_57766_FW_BASE_ADDR                 0x00030000
+#define TG3_57766_FW_HANDSHAKE                 0x0003fccc
+#define TG3_SBROM_IN_SERVICE_LOOP              0x51
+
 #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5700      128
 #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5755      64
 #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5906      32
@@ -2365,6 +2373,13 @@
 #define MII_TG3_FET_SHDW_AUXSTAT2      0x1b
 #define  MII_TG3_FET_SHDW_AUXSTAT2_APD 0x0020
 
+/* Serdes PHY Register Definitions */
+#define SERDES_TG3_1000X_STATUS                0x14
+#define  SERDES_TG3_SGMII_MODE          0x0001
+#define  SERDES_TG3_LINK_UP             0x0002
+#define  SERDES_TG3_FULL_DUPLEX                 0x0004
+#define  SERDES_TG3_SPEED_100           0x0008
+#define  SERDES_TG3_SPEED_1000          0x0010
 
 /* APE registers.  Accessible through BAR1 */
 #define TG3_APE_GPIO_MSG               0x0008
@@ -3065,6 +3080,13 @@ enum TG3_FLAGS {
        TG3_FLAG_NUMBER_OF_FLAGS,       /* Last entry in enum TG3_FLAGS */
 };
 
+struct tg3_firmware_hdr {
+       __be32 version; /* unused for fragments */
+       __be32 base_addr;
+       __be32 len;
+};
+#define TG3_FW_HDR_LEN         (sizeof(struct tg3_firmware_hdr))
+
 struct tg3 {
        /* begin "general, frequently-used members" cacheline section */
 
@@ -3268,6 +3290,7 @@ struct tg3 {
 #define TG3_PHYFLG_IS_LOW_POWER                0x00000001
 #define TG3_PHYFLG_IS_CONNECTED                0x00000002
 #define TG3_PHYFLG_USE_MI_INTERRUPT    0x00000004
+#define TG3_PHYFLG_USER_CONFIGURED     0x00000008
 #define TG3_PHYFLG_PHY_SERDES          0x00000010
 #define TG3_PHYFLG_MII_SERDES          0x00000020
 #define TG3_PHYFLG_ANY_SERDES          (TG3_PHYFLG_PHY_SERDES |        \
@@ -3285,6 +3308,8 @@ struct tg3 {
 #define TG3_PHYFLG_SERDES_PREEMPHASIS  0x00010000
 #define TG3_PHYFLG_PARALLEL_DETECT     0x00020000
 #define TG3_PHYFLG_EEE_CAP             0x00040000
+#define TG3_PHYFLG_1G_ON_VAUX_OK       0x00080000
+#define TG3_PHYFLG_KEEP_LINK_ON_PWRDN  0x00100000
 #define TG3_PHYFLG_MDIX_STATE          0x00200000
 
        u32                             led_ctrl;