{
u32 clk_rate;
- clk_rate = clk_get_rate(priv->stmmac_clk);
+ //clk_rate = clk_get_rate(priv->stmmac_clk);
+ clk_rate = clk_get_rate(priv->pclk);
/* Platform provided default clk_csr would be assumed valid
* for all other cases except for the below mentioned ones.
}
clk_prepare_enable(priv->stmmac_clk);
- priv->pclk = devm_clk_get(priv->device, "pclk");
+ //priv->pclk = devm_clk_get(priv->device, "pclk");
+ priv->pclk = devm_clk_get(priv->device, "pclk_mac");
if (IS_ERR(priv->pclk)) {
if (PTR_ERR(priv->pclk) == -EPROBE_DEFER) {
ret = -EPROBE_DEFER;
spin_lock_init(&priv->lock);
spin_lock_init(&priv->tx_lock);
- ret = register_netdev(ndev);
- if (ret) {
- pr_err("%s: ERROR %i registering the device\n", __func__, ret);
- goto error_netdev_register;
- }
-
/* If a specific clk_csr value is passed from the platform
* this means that the CSR Clock Range selection cannot be
* changed at run-time and it is fixed. Viceversa the driver'll try to
}
}
- return 0;
+ ret = register_netdev(ndev);
+ if (ret) {
+ netdev_err(priv->dev, "%s: ERROR %i registering the device\n",
+ __func__, ret);
+ goto error_netdev_register;
+ }
+
+ return ret;
-error_mdio_register:
- unregister_netdev(ndev);
error_netdev_register:
+ if (priv->pcs != STMMAC_PCS_RGMII &&
+ priv->pcs != STMMAC_PCS_TBI &&
+ priv->pcs != STMMAC_PCS_RTBI)
+ stmmac_mdio_unregister(ndev);
+error_mdio_register:
netif_napi_del(&priv->napi);
error_hw_init:
clk_disable_unprepare(priv->pclk);
stmmac_mdio_reset(priv->mii);
}
- netif_device_attach(ndev);
-
spin_lock_irqsave(&priv->lock, flags);
priv->cur_rx = 0;
netif_start_queue(ndev);
+ netif_device_attach(ndev);
+
spin_unlock_irqrestore(&priv->lock, flags);
if (priv->phydev)