net: emaclite: Code cleanup

[firefly-linux-kernel-4.4.55.git] / drivers / net / ethernet / xilinx / xilinx_emaclite.c

diff --git a/drivers/net/ethernet/xilinx/xilinx_emaclite.c b/drivers/net/ethernet/xilinx/xilinx_emaclite.c
index de3909878f426e147c58fe5c63c8e3e025d5621c..80dd404178505b02d599ab788e7c6152086d1728 100644 (file)
--- a/drivers/net/ethernet/xilinx/xilinx_emaclite.c
+++ b/drivers/net/ethernet/xilinx/xilinx_emaclite.c
@@ -31,7 +31,7 @@
 #define DRIVER_NAME "xilinx_emaclite"
 
 /* Register offsets for the EmacLite Core */
-#define XEL_TXBUFF_OFFSET      0x0             /* Transmit Buffer */
+#define XEL_TXBUFF_OFFSET      0x0             /* Transmit Buffer */
 #define XEL_MDIOADDR_OFFSET    0x07E4          /* MDIO Address Register */
 #define XEL_MDIOWR_OFFSET      0x07E8          /* MDIO Write Data Register */
 #define XEL_MDIORD_OFFSET      0x07EC          /* MDIO Read Data Register */
@@ -63,13 +63,13 @@
 #define XEL_MDIOCTRL_MDIOEN_MASK  0x00000008   /* MDIO Enable */
 
 /* Global Interrupt Enable Register (GIER) Bit Masks */
-#define XEL_GIER_GIE_MASK      0x80000000      /* Global Enable */
+#define XEL_GIER_GIE_MASK      0x80000000      /* Global Enable */
 
 /* Transmit Status Register (TSR) Bit Masks */
-#define XEL_TSR_XMIT_BUSY_MASK  0x00000001     /* Tx complete */
-#define XEL_TSR_PROGRAM_MASK    0x00000002     /* Program the MAC address */
-#define XEL_TSR_XMIT_IE_MASK    0x00000008     /* Tx interrupt enable bit */
-#define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000    /* Buffer is active, SW bit
+#define XEL_TSR_XMIT_BUSY_MASK  0x00000001     /* Tx complete */
+#define XEL_TSR_PROGRAM_MASK    0x00000002     /* Program the MAC address */
+#define XEL_TSR_XMIT_IE_MASK    0x00000008     /* Tx interrupt enable bit */
+#define XEL_TSR_XMIT_ACTIVE_MASK 0x80000000    /* Buffer is active, SW bit
                                                 * only. This is not documented
                                                 * in the HW spec */
 
@@ -77,21 +77,21 @@
 #define XEL_TSR_PROG_MAC_ADDR  (XEL_TSR_XMIT_BUSY_MASK | XEL_TSR_PROGRAM_MASK)
 
 /* Receive Status Register (RSR) */
-#define XEL_RSR_RECV_DONE_MASK 0x00000001      /* Rx complete */
-#define XEL_RSR_RECV_IE_MASK   0x00000008      /* Rx interrupt enable bit */
+#define XEL_RSR_RECV_DONE_MASK 0x00000001      /* Rx complete */
+#define XEL_RSR_RECV_IE_MASK   0x00000008      /* Rx interrupt enable bit */
 
 /* Transmit Packet Length Register (TPLR) */
-#define XEL_TPLR_LENGTH_MASK   0x0000FFFF      /* Tx packet length */
+#define XEL_TPLR_LENGTH_MASK   0x0000FFFF      /* Tx packet length */
 
 /* Receive Packet Length Register (RPLR) */
-#define XEL_RPLR_LENGTH_MASK   0x0000FFFF      /* Rx packet length */
+#define XEL_RPLR_LENGTH_MASK   0x0000FFFF      /* Rx packet length */
 
-#define XEL_HEADER_OFFSET      12              /* Offset to length field */
-#define XEL_HEADER_SHIFT       16              /* Shift value for length */
+#define XEL_HEADER_OFFSET      12              /* Offset to length field */
+#define XEL_HEADER_SHIFT       16              /* Shift value for length */
 
 /* General Ethernet Definitions */
-#define XEL_ARP_PACKET_SIZE            28      /* Max ARP packet size */
-#define XEL_HEADER_IP_LENGTH_OFFSET    16      /* IP Length Offset */
+#define XEL_ARP_PACKET_SIZE            28      /* Max ARP packet size */
+#define XEL_HEADER_IP_LENGTH_OFFSET    16      /* IP Length Offset */