\r
pDM_Odm->AntType = ODM_AUTO_ANT;\r
\r
- #if (MP_DRIVER == 1)\r
+#if (MP_DRIVER == 1)\r
pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;\r
ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv \r
ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); // 1:CG, 0:CS\r
return;\r
- #endif\r
+#else\r
\r
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init => AntDivType=[CGCS_RX_HW_ANTDIV]\n"));\r
\r
\r
ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , 0xFFFF, 0x0102); //antenna mapping table\r
\r
+#endif\r
}\r
\r
VOID\r
{\r
u4Byte value32;\r
\r
- #if (MP_DRIVER == 1)\r
+#if (MP_DRIVER == 1)\r
pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;\r
ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv \r
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, 0); //Default RX (0/1)\r
return;\r
- #endif\r
+#else\r
\r
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init => AntDivType=[CG_TRX_HW_ANTDIV (SPDT)]\n"));\r
\r
}\r
else //MPchip\r
ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , bMaskDWord, 0x0201); //Reg914=3'b010, Reg915=3'b001\r
+#endif\r
}\r
\r
VOID\r
#if (MP_DRIVER == 1)\r
ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("pDM_Odm->AntDivType: %d\n", pDM_Odm->AntDivType));\r
return;\r
-#endif\r
+#else\r
\r
for(i=0; i<6; i++)\r
{\r
//PHY_SetBBReg(Adapter, 0x864 , BIT11, 1);\r
//PHY_SetBBReg(Adapter, 0x860 , BIT9, 0);\r
//PHY_SetBBReg(Adapter, 0x860 , BIT8, 0);\r
+\r
+#endif\r
}\r
#endif //#if (RTL8188E_SUPPORT == 1)\r
\r
#if (RTL8821A_SUPPORT == 1)\r
else if(pDM_Odm->SupportICType == ODM_RTL8821)\r
{\r
- if(pDM_Odm->bBtDisabled) //BT disabled\r
+ if(!pDM_Odm->bBtEnabled) //BT disabled\r
{\r
if(pDM_Odm->AntDivType == S0S1_SW_ANTDIV)\r
{\r