#if 1//def CONFIG_SINGLE_IMG
-#include "../hal/OUTSRC/odm_precomp.h"
+#include "../hal/OUTSRC/phydm_precomp.h"
#ifdef CONFIG_BT_COEXIST
#include <hal_btcoex.h>
#endif
+#ifdef CONFIG_SDIO_HCI
+#include <hal_sdio.h>
+#endif
+#ifdef CONFIG_GSPI_HCI
+#include <hal_gspi.h>
+#endif
//
// <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06.
//
INTF_SEL5_USB_Combo_MF = 5, // USB WiFi+BT Multi-Function Combo, i.e., Proprietary layout(AS-VAU) which is the same as SDIO card
} INTERFACE_SELECT_USB, *PINTERFACE_SELECT_USB;
+#ifdef CONFIG_USB_HCI
+//should be sync with INTERFACE_SELECT_USB
+typedef enum _BOARD_TYPE_8192CUSB{
+ BOARD_USB_DONGLE = 0, // USB dongle
+ BOARD_USB_High_PA = 1, // USB dongle with high power PA
+ BOARD_MINICARD = 2, // Minicard
+ BOARD_USB_SOLO = 3, // USB solo-Slim module
+ BOARD_USB_COMBO = 4, // USB Combo-Slim module
+} BOARD_TYPE_8192CUSB, *PBOARD_TYPE_8192CUSB;
+
+#define SUPPORT_HW_RADIO_DETECT(pHalData) \
+ (pHalData->BoardType == BOARD_MINICARD||\
+ pHalData->BoardType == BOARD_USB_SOLO||\
+ pHalData->BoardType == BOARD_USB_COMBO)
+#endif
+
typedef enum _RT_AMPDU_BRUST_MODE{
RT_AMPDU_BRUST_NONE = 0,
RT_AMPDU_BRUST_92D = 1,
#endif
+#define PAGE_SIZE_128 128
+#define PAGE_SIZE_256 256
+#define PAGE_SIZE_512 512
+
struct dm_priv
{
u8 DM_Type;
// Add for Reading Initial Data Rate SEL Register 0x484 during watchdog. Using for fill tx desc. 2011.3.21 by Thomas
u8 INIDATA_RATE[32];
+ _lock IQKSpinLock;
};
u8 TxPwrLevelCck[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];
u8 TxPwrLevelHT40_1S[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
u8 TxPwrLevelHT40_2S[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; // For HT 40MHZ pwr
- u8 TxPwrHt20Diff[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff
+ s8 TxPwrHt20Diff[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];// HT 20<->40 Pwr diff
u8 TxPwrLegacyHtDiff[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];// For HT<->legacy pwr diff
// Power Limit Table for 2.4G
- u8 TxPwrLimit_2_4G[MAX_REGULATION_NUM]
+ s8 TxPwrLimit_2_4G[MAX_REGULATION_NUM]
[MAX_2_4G_BANDWITH_NUM]
[MAX_RATE_SECTION_NUM]
[CHANNEL_MAX_NUMBER_2G]
[MAX_RF_PATH_NUM];
// Power Limit Table for 5G
- u8 TxPwrLimit_5G[MAX_REGULATION_NUM]
+ s8 TxPwrLimit_5G[MAX_REGULATION_NUM]
[MAX_5G_BANDWITH_NUM]
[MAX_RATE_SECTION_NUM]
[CHANNEL_MAX_NUMBER_5G]
u8 RegReg542;
u8 RegCR_1;
u8 Reg837;
- u8 RegRFPathS1;
u16 RegRRSR;
u8 CurAntenna;
u8 AntDivCfg;
u8 AntDetection;
u8 TRxAntDivType;
+ u8 ant_path; //for 8723B s0/s1 selection
u8 u1ForcedIgiLb; // forced IGI lower bound
u8 p2p_ps_offload;
#endif
- u8 AMPDUDensity;
+ //u8 AMPDUDensity;
// Auto FSM to Turn On, include clock, isolation, power control for MAC only
u8 bMacPwrCtrlOn;
-
+ u8 bDisableTXPowerTraining;
u8 RegIQKFWOffload;
struct submit_ctx iqk_sctx;
RT_AMPDU_BRUST AMPDUBurstMode; //92C maybe not use, but for compile successfully
-#ifdef CONFIG_SDIO_HCI
+#if defined (CONFIG_SDIO_HCI) || defined(CONFIG_GSPI_HCI)
//
// For SDIO Interface HAL related
//
// HIQ, MID, LOW, PUB free pages; padapter->xmitpriv.free_txpg
u8 SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE];
_lock SdioTxFIFOFreePageLock;
+ u8 SdioTxOQTMaxFreeSpace;
+ u8 SdioTxOQTFreeSpace;
+
//
// SDIO Rx FIFO related.
//
u8 SdioRxFIFOCnt;
u16 SdioRxFIFOSize;
+
+ u32 sdio_tx_max_len[SDIO_MAX_TX_QUEUE];// H, N, L, used for sdio tx aggregation max length per queue
#endif //CONFIG_SDIO_HCI
#ifdef CONFIG_USB_HCI
u8 bInterruptMigration;
u8 bDisableTxInt;
- u8 bGpioHwWpsPbc;
+
+ u16 RxTag;
#endif //CONFIG_PCI_HCI
struct dm_priv dmpriv;
#endif // CONFIG_BT_COEXIST
#if defined(CONFIG_RTL8723A) || defined(CONFIG_RTL8723B)
+ #ifndef CONFIG_PCI_HCI // mutual exclusive with PCI -- so they're SDIO and GSPI
// Interrupt relatd register information.
u32 SysIntrStatus;
u32 SysIntrMask;
+ #endif
#endif //endif CONFIG_RTL8723A
char *rf_tx_pwr_lmt;
u32 rf_tx_pwr_lmt_len;
#endif
+
+#ifdef CONFIG_BACKGROUND_NOISE_MONITOR
+ s16 noise[ODM_MAX_CHANNEL_NUM];
+#endif
+
+ u8 macid_num;
+ u8 cam_entry_num;
+
} HAL_DATA_COMMON, *PHAL_DATA_COMMON;