#ifndef __HAL_PG_H__\r
#define __HAL_PG_H__\r
\r
-//====================================================\r
-// EEPROM/Efuse PG Offset for 8192 CE/CU\r
-//====================================================\r
-#define EEPROM_VID_92C 0x0A\r
-#define EEPROM_PID_92C 0x0C\r
-#define EEPROM_DID_92C 0x0C \r
-#define EEPROM_SVID_92C 0x0E\r
-#define EEPROM_SMID_92C 0x10 \r
-#define EEPROM_MAC_ADDR_92C 0x16\r
-\r
-#define EEPROM_MAC_ADDR 0x16\r
-#define EEPROM_TV_OPTION 0x50\r
-#define EEPROM_SUBCUSTOMER_ID_92C 0x59\r
-#define EEPROM_CCK_TX_PWR_INX 0x5A\r
-#define EEPROM_HT40_1S_TX_PWR_INX 0x60\r
-#define EEPROM_HT40_2S_TX_PWR_INX_DIFF 0x66\r
-#define EEPROM_HT20_TX_PWR_INX_DIFF 0x69\r
-#define EEPROM_OFDM_TX_PWR_INX_DIFF 0x6C\r
-#define EEPROM_HT40_MAX_PWR_OFFSET 0x6F\r
-#define EEPROM_HT20_MAX_PWR_OFFSET 0x72\r
-#define EEPROM_CHANNEL_PLAN_92C 0x75\r
-#define EEPROM_TSSI_A 0x76\r
-#define EEPROM_TSSI_B 0x77\r
-#define EEPROM_THERMAL_METER_92C 0x78\r
-#define EEPROM_RF_OPT1_92C 0x79\r
-#define EEPROM_RF_OPT2_92C 0x7A\r
-#define EEPROM_RF_OPT3_92C 0x7B\r
-#define EEPROM_RF_OPT4_92C 0x7C\r
-#define EEPROM_VERSION_92C 0x7E\r
-#define EEPROM_CUSTOMER_ID_92C 0x7F\r
-\r
-#define EEPROM_NORMAL_CHANNEL_PLAN 0x75\r
-#define EEPROM_NORMAL_BoardType_92C EEPROM_RF_OPT1_92C\r
-#define BOARD_TYPE_NORMAL_MASK 0xE0\r
-#define BOARD_TYPE_TEST_MASK 0xF\r
-#define EEPROM_TYPE_ID 0x7E\r
-\r
-// PCIe related\r
-#define EEPROM_PCIE_DEV_CAP_01 0xE0 // Express device capability in PCIe configuration space, i.e., map to offset 0x74\r
-#define EEPROM_PCIE_DEV_CAP_02 0xE1 // Express device capability in PCIe configuration space, i.e., map to offset 0x75\r
-\r
-// EEPROM address for Test chip\r
-#define EEPROM_TEST_USB_OPT 0x0E\r
-\r
-#define EEPROM_EASY_REPLACEMENT 0x50//BIT0 1 for build-in module, 0 for external dongle\r
+#define PPG_BB_GAIN_2G_TX_OFFSET_MASK 0x0F\r
+#define PPG_BB_GAIN_2G_TXB_OFFSET_MASK 0xF0\r
\r
-//====================================================\r
-// EEPROM/Efuse PG Offset for 8723AE/8723AU/8723AS\r
-//====================================================\r
-#define EEPROM_CCK_TX_PWR_INX_8723A 0x10\r
-#define EEPROM_HT40_1S_TX_PWR_INX_8723A 0x16\r
-#define EEPROM_HT20_TX_PWR_INX_DIFF_8723A 0x1C\r
-#define EEPROM_OFDM_TX_PWR_INX_DIFF_8723A 0x1F\r
-#define EEPROM_HT40_MAX_PWR_OFFSET_8723A 0x22 \r
-#define EEPROM_HT20_MAX_PWR_OFFSET_8723A 0x25 \r
-\r
-#define EEPROM_ChannelPlan_8723A 0x28\r
-#define EEPROM_TSSI_A_8723A 0x29\r
-#define EEPROM_THERMAL_METER_8723A 0x2A\r
-#define RF_OPTION1_8723A 0x2B\r
-#define RF_OPTION2_8723A 0x2C\r
-#define RF_OPTION3_8723A 0x2D\r
-#define RF_OPTION4_8723A 0x2E\r
-#define EEPROM_VERSION_8723A 0x30\r
-#define EEPROM_CustomID_8723A 0x31\r
-#define EEPROM_SubCustomID_8723A 0x32\r
-#define EEPROM_XTAL_K_8723A 0x33\r
-#define EEPROM_Chipset_8723A 0x34\r
-\r
-\r
-// RTL8723AE\r
-#define EEPROM_VID_8723AE 0x49\r
-#define EEPROM_DID_8723AE 0x4B\r
-#define EEPROM_SVID_8723AE 0x4D\r
-#define EEPROM_SMID_8723AE 0x4F\r
-#define EEPROM_MAC_ADDR_8723AE 0x67\r
-\r
-//RTL8723AU\r
-#define EEPROM_MAC_ADDR_8723AU 0xC6\r
-#define EEPROM_VID_8723AU 0xB7\r
-#define EEPROM_PID_8723AU 0xB9\r
-\r
-// RTL8723AS\r
-#define EEPROM_MAC_ADDR_8723AS 0xAA\r
-\r
-//====================================================\r
-// EEPROM/Efuse PG Offset for 8192 DE/DU\r
-//====================================================\r
-// pcie\r
-#define RTL8190_EEPROM_ID 0x8129 // 0-1\r
-#define EEPROM_HPON 0x02 // LDO settings.2-5\r
-#define EEPROM_CLK 0x06 // Clock settings.6-7\r
-#define EEPROM_MAC_FUNCTION 0x08 // SE Test mode.8\r
-\r
-#define EEPROM_MAC_ADDR_MAC0_92DE 0x55\r
-#define EEPROM_MAC_ADDR_MAC1_92DE 0x5B\r
-\r
-//usb\r
-#define EEPROM_ENDPOINT_SETTING 0x10\r
-#define EEPROM_CHIRP_K 0x12 // Changed\r
-#define EEPROM_USB_PHY 0x13 // Changed\r
-#define EEPROM_STRING 0x1F\r
-#define EEPROM_SUBCUSTOMER_ID_92D 0x59\r
-\r
-#define EEPROM_MAC_ADDR_MAC0_92DU 0x19\r
-#define EEPROM_MAC_ADDR_MAC1_92DU 0x5B\r
-//----------------------------------------------------------------\r
-// 2.4G band Tx power index setting\r
-#define EEPROM_CCK_TX_PWR_INX_2G_92D 0x61\r
-#define EEPROM_HT40_1S_TX_PWR_INX_2G_92D 0x67\r
-#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G_92D 0x6D\r
-#define EEPROM_HT20_TX_PWR_INX_DIFF_2G_92D 0x70\r
-#define EEPROM_OFDM_TX_PWR_INX_DIFF_2G_92D 0x73\r
-#define EEPROM_HT40_MAX_PWR_OFFSET_2G_92D 0x76\r
-#define EEPROM_HT20_MAX_PWR_OFFSET_2G_92D 0x79\r
-\r
-//5GL channel 32-64\r
-#define EEPROM_HT40_1S_TX_PWR_INX_5GL_92D 0x7C\r
-#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GL_92D 0x82\r
-#define EEPROM_HT20_TX_PWR_INX_DIFF_5GL_92D 0x85\r
-#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GL_92D 0x88\r
-#define EEPROM_HT40_MAX_PWR_OFFSET_5GL_92D 0x8B\r
-#define EEPROM_HT20_MAX_PWR_OFFSET_5GL_92D 0x8E\r
-\r
-//5GM channel 100-140\r
-#define EEPROM_HT40_1S_TX_PWR_INX_5GM_92D 0x91\r
-#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GM_92D 0x97\r
-#define EEPROM_HT20_TX_PWR_INX_DIFF_5GM_92D 0x9A\r
-#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GM_92D 0x9D\r
-#define EEPROM_HT40_MAX_PWR_OFFSET_5GM_92D 0xA0\r
-#define EEPROM_HT20_MAX_PWR_OFFSET_5GM_92D 0xA3\r
-\r
-//5GH channel 149-165\r
-#define EEPROM_HT40_1S_TX_PWR_INX_5GH_92D 0xA6\r
-#define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GH_92D 0xAC\r
-#define EEPROM_HT20_TX_PWR_INX_DIFF_5GH_92D 0xAF\r
-#define EEPROM_OFDM_TX_PWR_INX_DIFF_5GH_92D 0xB2\r
-#define EEPROM_HT40_MAX_PWR_OFFSET_5GH_92D 0xB5\r
-#define EEPROM_HT20_MAX_PWR_OFFSET_5GH_92D 0xB8\r
-\r
-\r
-#define EEPROM_CHANNEL_PLAN_92D 0xBB // Map of supported channels. \r
-#define EEPROM_TEST_CHANNEL_PLAN_92D 0xBB\r
-#define EEPROM_THERMAL_METER_92D 0xC3 //[4:0]\r
-#define EEPROM_IQK_DELTA_92D 0xBC\r
-#define EEPROM_LCK_DELTA_92D 0xBC\r
-#define EEPROM_XTAL_K_92D 0xBD //[7:5]\r
-#define EEPROM_TSSI_A_5G_92D 0xBE\r
-#define EEPROM_TSSI_B_5G_92D 0xBF\r
-#define EEPROM_TSSI_AB_5G_92D 0xC0\r
-\r
-#define EEPROM_RF_OPT1_92D 0xC4\r
-#define EEPROM_RF_OPT2_92D 0xC5\r
-#define EEPROM_RF_OPT3_92D 0xC6\r
-#define EEPROM_RF_OPT4_92D 0xC7\r
-#define EEPROM_RF_OPT5_92D 0xC8\r
-#define EEPROM_RF_OPT6_92D 0xC9\r
-#define EEPROM_RF_OPT7_92D 0xCC\r
-\r
-#define EEPROM_NORMAL_BoardType_92D EEPROM_RF_OPT1_92D //[7:5]\r
-\r
-#define EEPROM_WIDIPAIRING_ADDR 0xF0\r
-#define EEPROM_WIDIPAIRING_KEY 0xF6\r
-\r
-#define EEPROM_DEF_PART_NO 0x3FD //Byte\r
-#define EEPROME_CHIP_VERSION_L 0x3FF\r
-#define EEPROME_CHIP_VERSION_H 0x3FE\r
-\r
-//----------------------------------------------------------------\r
-\r
-#define EEPROM_VID_92DE 0x28\r
-#define EEPROM_PID_92DE 0x2A\r
-#define EEPROM_SVID_92DE 0x2C\r
-#define EEPROM_SMID_92DE 0x2E\r
-#define EEPROM_PATHDIV_92D 0xC4\r
-\r
-#define EEPROM_BOARD_OPTIONS_92D 0xC4\r
-#define EEPROM_5G_LNA_GAIN_92D 0xC6\r
-#define EEPROM_FEATURE_OPTIONS_92D 0xC7\r
-#define EEPROM_BT_SETTING_92D 0xC8\r
-\r
-#define EEPROM_VERSION_92D 0xCA\r
-#define EEPROM_CUSTOMER_ID_92D 0xCB\r
-\r
-#define EEPROM_VID_92DU 0xC\r
-#define EEPROM_PID_92DU 0xE\r
+#define PPG_BB_GAIN_5G_TX_OFFSET_MASK 0x1F\r
+#define PPG_THERMAL_OFFSET_MASK 0x1F\r
+#define KFREE_BB_GAIN_2G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_2G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg_v) >> 1) : (-((_ppg_v) >> 1))))\r
+#define KFREE_BB_GAIN_5G_TX_OFFSET(_ppg_v) (((_ppg_v) == PPG_BB_GAIN_5G_TX_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg_v) >> 1) : (-((_ppg_v) >> 1))))\r
+#define KFREE_THERMAL_OFFSET(_ppg_v) (((_ppg_v) == PPG_THERMAL_OFFSET_MASK) ? 0 : (((_ppg_v) & 0x01) ? ((_ppg_v) >> 1) : (-((_ppg_v) >> 1))))\r
\r
//====================================================\r
// EEPROM/Efuse PG Offset for 88EE/88EU/88ES\r
#define EEPROM_VERSION_88E 0xC4\r
#define EEPROM_CustomID_88E 0xC5\r
#define EEPROM_RF_ANTENNA_OPT_88E 0xC9\r
+#define EEPROM_COUNTRY_CODE_88E 0xCB\r
\r
// RTL88EE\r
#define EEPROM_MAC_ADDR_88EE 0xD0\r
#define EEPROM_MAC_ADDR_88EU 0xD7\r
#define EEPROM_VID_88EU 0xD0\r
#define EEPROM_PID_88EU 0xD2\r
-#define EEPROM_USB_OPTIONAL_FUNCTION0 0xD4 //8192EU, 8812AU is the same\r
+#define EEPROM_USB_OPTIONAL_FUNCTION0 0xD4 //8188EU,8192EU, 8812AU is the same\r
#define EEPROM_USB_OPTIONAL_FUNCTION0_8811AU 0x104\r
\r
// RTL88ES\r
//====================================================\r
// EEPROM/Efuse PG Offset for 8192EE/8192EU/8192ES\r
//====================================================\r
+#define GET_PG_KFREE_ON_8192E(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1)\r
+#define GET_PG_KFREE_THERMAL_K_ON_8192E(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)\r
+\r
+#define PPG_BB_GAIN_2G_TXA_OFFSET_8192E 0x1F6\r
+#define PPG_THERMAL_OFFSET_8192E 0x1F5\r
+\r
// 0x10 ~ 0x63 = TX power area.\r
#define EEPROM_TX_PWR_INX_8192E 0x10\r
\r
#define EEPROM_TX_BBSWING_5G_8192E 0xC7\r
#define EEPROM_TX_PWR_CALIBRATE_RATE_8192E 0xC8\r
#define EEPROM_RF_ANTENNA_OPT_8192E 0xC9\r
+#define EEPROM_RFE_OPTION_8192E 0xCA
+#define EEPROM_RFE_OPTION_8188E 0xCA\r
+#define EEPROM_COUNTRY_CODE_8192E 0xCB\r
\r
// RTL8192EE\r
#define EEPROM_MAC_ADDR_8192EE 0xD0\r
#define EEPROM_LNA_TYPE_5G_8192EU 0xBF\r
\r
// RTL8192ES\r
-#define EEPROM_MAC_ADDR_8192ES 0x11B\r
+#define EEPROM_MAC_ADDR_8192ES 0x11A\r
//====================================================\r
// EEPROM/Efuse PG Offset for 8812AE/8812AU/8812AS\r
//====================================================\r
#define EEPROM_TX_PWR_CALIBRATE_RATE_8812 0xC8\r
#define EEPROM_RF_ANTENNA_OPT_8812 0xC9\r
#define EEPROM_RFE_OPTION_8812 0xCA\r
+#define EEPROM_COUNTRY_CODE_8812 0xCB\r
\r
// RTL8812AE\r
#define EEPROM_MAC_ADDR_8812AE 0xD0\r
#define EEPROM_LNA_TYPE_2G_8812AU 0xBD\r
#define EEPROM_LNA_TYPE_5G_8812AU 0xBF\r
\r
+//RTL8814AU\r
+#define EEPROM_MAC_ADDR_8814AU 0xD8\r
+#define EEPROM_VID_8814AU 0xD0\r
+#define EEPROM_PID_8814AU 0xD2\r
+#define EEPROM_PA_TYPE_8814AU 0xBC\r
+#define EEPROM_LNA_TYPE_2G_8814AU 0xBD\r
+#define EEPROM_LNA_TYPE_5G_8814AU 0xBF\r
+\r
+/* RTL8814AE */\r
+#define EEPROM_MAC_ADDR_8814AE 0xD0\r
+#define EEPROM_VID_8814AE 0xD6\r
+#define EEPROM_DID_8814AE 0xD8\r
+#define EEPROM_SVID_8814AE 0xDA\r
+#define EEPROM_SMID_8814AE 0xDC\r
+\r
+//====================================================\r
+// EEPROM/Efuse PG Offset for 8814AU\r
+//====================================================\r
+#define GET_PG_KFREE_ON_8814A(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 4, 1)\r
+#define GET_PG_KFREE_THERMAL_K_ON_8814A(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)\r
+#define GET_PG_TX_POWER_TRACKING_MODE_8814A(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 6, 2)\r
+\r
+#define KFREE_GAIN_DATA_LENGTH_8814A 22\r
+\r
+#define PPG_BB_GAIN_2G_TXBA_OFFSET_8814A 0x3EE\r
+\r
+#define PPG_THERMAL_OFFSET_8814A 0x3EF\r
+\r
+#define EEPROM_TX_PWR_INX_8814 0x10\r
+#define EEPROM_ChannelPlan_8814 0xB8\r
+#define EEPROM_XTAL_8814 0xB9\r
+#define EEPROM_THERMAL_METER_8814 0xBA\r
+#define EEPROM_IQK_LCK_8814 0xBB\r
+\r
+\r
+#define EEPROM_PA_TYPE_8814 0xBC\r
+#define EEPROM_LNA_TYPE_AB_2G_8814 0xBD\r
+#define EEPROM_LNA_TYPE_CD_2G_8814 0xBE\r
+#define EEPROM_LNA_TYPE_AB_5G_8814 0xBF\r
+#define EEPROM_LNA_TYPE_CD_5G_8814 0xC0\r
+#define EEPROM_RF_BOARD_OPTION_8814 0xC1\r
+#define EEPROM_RF_BT_SETTING_8814 0xC3\r
+#define EEPROM_VERSION_8814 0xC4\r
+#define EEPROM_CustomID_8814 0xC5\r
+#define EEPROM_TX_BBSWING_2G_8814 0xC6\r
+#define EEPROM_TX_BBSWING_5G_8814 0xC7\r
+#define EEPROM_TRX_ANTENNA_OPTION_8814 0xC9\r
+#define EEPROM_RFE_OPTION_8814 0xCA\r
+#define EEPROM_COUNTRY_CODE_8814 0xCB\r
+\r
+/*Extra Info for 8814A Initial Gain Fine Tune suggested by Willis, JIRA: MP123*/\r
+#define EEPROM_IG_OFFSET_4_AB_2G_8814A 0x120\r
+#define EEPROM_IG_OFFSET_4_CD_2G_8814A 0x121\r
+#define EEPROM_IG_OFFSET_4_AB_5GL_8814A 0x122\r
+#define EEPROM_IG_OFFSET_4_CD_5GL_8814A 0x123\r
+#define EEPROM_IG_OFFSET_4_AB_5GM_8814A 0x124\r
+#define EEPROM_IG_OFFSET_4_CD_5GM_8814A 0x125\r
+#define EEPROM_IG_OFFSET_4_AB_5GH_8814A 0x126\r
+#define EEPROM_IG_OFFSET_4_CD_5GH_8814A 0x127\r
+\r
//====================================================\r
// EEPROM/Efuse PG Offset for 8821AE/8821AU/8821AS\r
//====================================================\r
+\r
+#define GET_PG_KFREE_ON_8821A(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 4, 1)\r
+#define GET_PG_KFREE_THERMAL_K_ON_8821A(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)\r
+\r
+#define PPG_BB_GAIN_2G_TXA_OFFSET_8821A 0x1F6\r
+#define PPG_THERMAL_OFFSET_8821A 0x1F5\r
+#define PPG_BB_GAIN_5GLB1_TXA_OFFSET_8821A 0x1F4\r
+#define PPG_BB_GAIN_5GLB2_TXA_OFFSET_8821A 0x1F3\r
+#define PPG_BB_GAIN_5GMB1_TXA_OFFSET_8821A 0x1F2\r
+#define PPG_BB_GAIN_5GMB2_TXA_OFFSET_8821A 0x1F1\r
+#define PPG_BB_GAIN_5GHB_TXA_OFFSET_8821A 0x1F0\r
+\r
#define EEPROM_TX_PWR_INX_8821 0x10\r
\r
#define EEPROM_ChannelPlan_8821 0xB8\r
#define EEPROM_TSSI_A_92SU 0x6b \r
#define EEPROM_TSSI_B_92SU 0x6c \r
\r
+/* ====================================================\r
+ EEPROM/Efuse PG Offset for 8188FE/8188FU/8188FS\r
+ ====================================================\r
+ */\r
+\r
+#define GET_PG_KFREE_ON_8188F(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1)\r
+#define GET_PG_KFREE_THERMAL_K_ON_8188F(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)\r
+\r
+#define PPG_BB_GAIN_2G_TXA_OFFSET_8188F 0xEE\r
+#define PPG_THERMAL_OFFSET_8188F 0xEF\r
+\r
+/* 0x10 ~ 0x63 = TX power area. */\r
+#define EEPROM_TX_PWR_INX_8188F 0x10\r
+\r
+#define EEPROM_ChannelPlan_8188F 0xB8\r
+#define EEPROM_XTAL_8188F 0xB9\r
+#define EEPROM_THERMAL_METER_8188F 0xBA\r
+#define EEPROM_IQK_LCK_8188F 0xBB\r
+#define EEPROM_2G_5G_PA_TYPE_8188F 0xBC\r
+#define EEPROM_2G_LNA_TYPE_GAIN_SEL_8188F 0xBD\r
+#define EEPROM_5G_LNA_TYPE_GAIN_SEL_8188F 0xBF\r
+\r
+#define EEPROM_RF_BOARD_OPTION_8188F 0xC1\r
+#define EEPROM_FEATURE_OPTION_8188F 0xC2\r
+#define EEPROM_RF_BT_SETTING_8188F 0xC3\r
+#define EEPROM_VERSION_8188F 0xC4\r
+#define EEPROM_CustomID_8188F 0xC5\r
+#define EEPROM_TX_BBSWING_2G_8188F 0xC6\r
+#define EEPROM_TX_PWR_CALIBRATE_RATE_8188F 0xC8\r
+#define EEPROM_RF_ANTENNA_OPT_8188F 0xC9\r
+#define EEPROM_RFE_OPTION_8188F 0xCA\r
+#define EEPROM_COUNTRY_CODE_8188F 0xCB\r
+#define EEPROM_CUSTOMER_ID_8188F 0x7F\r
+#define EEPROM_SUBCUSTOMER_ID_8188F 0x59\r
+\r
+/* RTL8188FU */\r
+#define EEPROM_MAC_ADDR_8188FU 0xD7\r
+#define EEPROM_VID_8188FU 0xD0\r
+#define EEPROM_PID_8188FU 0xD2\r
+#define EEPROM_PA_TYPE_8188FU 0xBC\r
+#define EEPROM_LNA_TYPE_2G_8188FU 0xBD\r
+#define EEPROM_USB_OPTIONAL_FUNCTION0_8188FU 0xD4\r
+\r
+/* RTL8188FS */\r
+#define EEPROM_MAC_ADDR_8188FS 0x11A\r
+#define EEPROM_Voltage_ADDR_8188F 0x8\r
+\r
//====================================================\r
// EEPROM/Efuse PG Offset for 8723BE/8723BU/8723BS\r
//====================================================\r
#define EEPROM_TX_PWR_CALIBRATE_RATE_8723B 0xC8\r
#define EEPROM_RF_ANTENNA_OPT_8723B 0xC9\r
#define EEPROM_RFE_OPTION_8723B 0xCA\r
+#define EEPROM_COUNTRY_CODE_8723B 0xCB\r
\r
// RTL8723BE\r
#define EEPROM_MAC_ADDR_8723BE 0xD0\r
#define EEPROM_PA_TYPE_8723BU 0xBC\r
#define EEPROM_LNA_TYPE_2G_8723BU 0xBD\r
\r
+\r
//RTL8723BS\r
#define EEPROM_MAC_ADDR_8723BS 0x11A\r
#define EEPROM_Voltage_ADDR_8723B 0x8\r
\r
+//====================================================\r
+/* EEPROM/Efuse PG Offset for 8703B */\r
+//====================================================\r
+#define GET_PG_KFREE_ON_8703B(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC1, 4, 1)\r
+#define GET_PG_KFREE_THERMAL_K_ON_8703B(_pg_m) LE_BITS_TO_1BYTE(((u8 *)(_pg_m)) + 0xC8, 5, 1)\r
+\r
+#define PPG_BB_GAIN_2G_TXA_OFFSET_8703B 0xEE\r
+#define PPG_THERMAL_OFFSET_8703B 0xEF\r
+\r
+#define EEPROM_TX_PWR_INX_8703B 0x10\r
+\r
+#define EEPROM_ChannelPlan_8703B 0xB8\r
+#define EEPROM_XTAL_8703B 0xB9\r
+#define EEPROM_THERMAL_METER_8703B 0xBA\r
+#define EEPROM_IQK_LCK_8703B 0xBB\r
+#define EEPROM_2G_5G_PA_TYPE_8703B 0xBC\r
+#define EEPROM_2G_LNA_TYPE_GAIN_SEL_8703B 0xBD\r
+#define EEPROM_5G_LNA_TYPE_GAIN_SEL_8703B 0xBF\r
+\r
+#define EEPROM_RF_BOARD_OPTION_8703B 0xC1\r
+#define EEPROM_FEATURE_OPTION_8703B 0xC2\r
+#define EEPROM_RF_BT_SETTING_8703B 0xC3\r
+#define EEPROM_VERSION_8703B 0xC4\r
+#define EEPROM_CustomID_8703B 0xC5\r
+#define EEPROM_TX_BBSWING_2G_8703B 0xC6\r
+#define EEPROM_TX_PWR_CALIBRATE_RATE_8703B 0xC8\r
+#define EEPROM_RF_ANTENNA_OPT_8703B 0xC9\r
+#define EEPROM_RFE_OPTION_8703B 0xCA\r
+#define EEPROM_COUNTRY_CODE_8703B 0xCB\r
+\r
+/* MAC Hidden */\r
+#define PPG_MAC_HIDDEN_START_8703B 0xF0\r
+#define PPG_MAC_HIDDEN_END_8703B 0xFF\r
+#define EEPROM_HCI_AND_PACKAGE_TYPE_8703B 0xF8\r
+#define EEPROM_WL_FUNC_CAP_8703B 0xF9\r
+#define EEPROM_BW_AND_ANT_NUM_CAP_8703B 0xFB\r
+#define GET_PMH_HCI_TYPE_8703B(_pmh_m) LE_BITS_TO_1BYTE(((u8 *)(_pmh_m)) + EEPROM_HCI_AND_PACKAGE_TYPE_8703B - PPG_MAC_HIDDEN_START_8703B, 0, 4)\r
+#define GET_PMH_PACKAGE_TYPE_8703B(_pmh_m) LE_BITS_TO_1BYTE(((u8 *)(_pmh_m)) + EEPROM_HCI_AND_PACKAGE_TYPE_8703B - PPG_MAC_HIDDEN_START_8703B, 4, 4)\r
+#define GET_PMH_WL_FUNC_CAP_8703B(_pmh_m) LE_BITS_TO_1BYTE(((u8 *)(_pmh_m)) + EEPROM_WL_FUNC_CAP_8703B - PPG_MAC_HIDDEN_START_8703B, 0, 4)\r
+#define GET_PMH_BW_CAP_8703B(_pmh_m) LE_BITS_TO_1BYTE(((u8 *)(_pmh_m)) + EEPROM_BW_AND_ANT_NUM_CAP_8703B - PPG_MAC_HIDDEN_START_8703B, 0, 3)\r
+#define GET_PMH_ANT_NUM_CAP_8703B(_pmh_m) LE_BITS_TO_1BYTE(((u8 *)(_pmh_m)) + EEPROM_BW_AND_ANT_NUM_CAP_8703B - PPG_MAC_HIDDEN_START_8703B, 5, 3)\r
+\r
+/* RTL8703BU */\r
+#define EEPROM_MAC_ADDR_8703BU 0x107\r
+#define EEPROM_VID_8703BU 0x100\r
+#define EEPROM_PID_8703BU 0x102\r
+#define EEPROM_USB_OPTIONAL_FUNCTION0_8703BU 0x104\r
+#define EEPROM_PA_TYPE_8703BU 0xBC\r
+#define EEPROM_LNA_TYPE_2G_8703BU 0xBD\r
+\r
+//RTL8703BS\r
+#define EEPROM_MAC_ADDR_8703BS 0x11A\r
+#define EEPROM_Voltage_ADDR_8703B 0x8\r
\r
//====================================================\r
// EEPROM/Efuse Value Type\r
#define EEPROM_Default_ThermalMeter_8812 0x18\r
#define EEPROM_Default_ThermalMeter_8192E 0x1A\r
#define EEPROM_Default_ThermalMeter_8723B 0x18\r
+#define EEPROM_Default_ThermalMeter_8703B 0x18\r
+#define EEPROM_Default_ThermalMeter_8188F 0x18\r
+#define EEPROM_Default_ThermalMeter_8814A 0x18\r
\r
\r
#define EEPROM_Default_CrystalCap 0x0\r
#define EEPROM_Default_CrystalCap_8723A 0x20\r
#define EEPROM_Default_CrystalCap_88E 0x20\r
#define EEPROM_Default_CrystalCap_8812 0x20\r
+#define EEPROM_Default_CrystalCap_8814 0x20\r
#define EEPROM_Default_CrystalCap_8192E 0x20\r
#define EEPROM_Default_CrystalCap_8723B 0x20\r
+#define EEPROM_Default_CrystalCap_8703B 0x20\r
+#define EEPROM_Default_CrystalCap_8188F 0x20\r
#define EEPROM_Default_CrystalFreq 0x0\r
#define EEPROM_Default_TxPowerLevel_92C 0x22\r
#define EEPROM_Default_TxPowerLevel_2G 0x2C\r
#define EEPROM_DEFAULT_DIFF 0XFE\r
#define EEPROM_DEFAULT_CHANNEL_PLAN 0x7F\r
#define EEPROM_DEFAULT_BOARD_OPTION 0x00\r
+#define EEPROM_DEFAULT_RFE_OPTION_8192E 0xFF\r
+#define EEPROM_DEFAULT_RFE_OPTION_8188E 0xFF\r
#define EEPROM_DEFAULT_RFE_OPTION 0x04\r
#define EEPROM_DEFAULT_FEATURE_OPTION 0x00\r
#define EEPROM_DEFAULT_BT_OPTION 0x10\r
\r
#define EEPROM_DEFAULT_TX_CALIBRATE_RATE 0x00\r
\r
+// PCIe related\r
+#define EEPROM_PCIE_DEV_CAP_01 0xE0 // Express device capability in PCIe configuration space, i.e., map to offset 0x74\r
+#define EEPROM_PCIE_DEV_CAP_02 0xE1 // Express device capability in PCIe configuration space, i.e., map to offset 0x75\r
+\r
+\r
//\r
// For VHT series TX power by rate table.\r
// VHT TX power by rate off setArray = \r
//----------------------------------------------------------------------------\r
// EEPROM/EFUSE data structure definition.\r
//----------------------------------------------------------------------------\r
-#define MAX_RF_PATH_NUM 2\r
-#define MAX_CHNL_GROUP 3+9\r
-typedef struct _TxPowerInfo{\r
- u8 CCKIndex[MAX_RF_PATH_NUM][MAX_CHNL_GROUP];\r
- u8 HT40_1SIndex[MAX_RF_PATH_NUM][MAX_CHNL_GROUP];\r
- u8 HT40_2SIndexDiff[MAX_RF_PATH_NUM][MAX_CHNL_GROUP];\r
- s8 HT20IndexDiff[MAX_RF_PATH_NUM][MAX_CHNL_GROUP];\r
- u8 OFDMIndexDiff[MAX_RF_PATH_NUM][MAX_CHNL_GROUP];\r
- u8 HT40MaxOffset[MAX_RF_PATH_NUM][MAX_CHNL_GROUP];\r
- u8 HT20MaxOffset[MAX_RF_PATH_NUM][MAX_CHNL_GROUP];\r
- u8 TSSI_A[3];\r
- u8 TSSI_B[3];\r
- u8 TSSI_A_5G[3]; //5GL/5GM/5GH\r
- u8 TSSI_B_5G[3];\r
-}TxPowerInfo, *PTxPowerInfo;\r
-\r
\r
//For 88E new structure\r
\r
}\r
*/\r
#define MAX_RF_PATH 4\r
-#define RF_PATH_MAX MAX_RF_PATH \r
+#define RF_PATH_MAX MAX_RF_PATH \r
#define MAX_CHNL_GROUP_24G 6 \r
#define MAX_CHNL_GROUP_5G 14 \r
\r
BT_RTL8821 = 7,\r
BT_RTL8723B = 8,\r
BT_RTL8192E = 9,\r
- BT_RTL8813A = 10,\r
- BT_RTL8812A = 11\r
+ BT_RTL8814A = 10,\r
+ BT_RTL8812A = 11,\r
+ BT_RTL8703B = 12\r
} BT_CoType, *PBT_CoType;\r
\r
typedef enum _BT_RadioShared{\r
projects / firefly-linux-kernel-4.4.55.git / blobdiff