//======================================================\r
VOID\r
ODM_StopAntennaSwitchDm(\r
- IN PDM_ODM_T pDM_Odm\r
+ IN PVOID pDM_VOID\r
)\r
{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
// disable ODM antenna diversity\r
pDM_Odm->SupportAbility &= ~ODM_BB_ANT_DIV;\r
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("STOP Antenna Diversity \n"));\r
\r
VOID\r
ODM_SetAntConfig(\r
- IN PDM_ODM_T pDM_Odm,\r
+ IN PVOID pDM_VOID,\r
IN u1Byte antSetting // 0=A, 1=B, 2=C, ....\r
)\r
{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
if(pDM_Odm->SupportICType == ODM_RTL8723B)\r
{\r
if(antSetting == 0) // ant A\r
//======================================================\r
\r
\r
-VOID
-ODM_SwAntDivRestAfterLink(
- IN PDM_ODM_T pDM_Odm
- )
-{
- pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
- pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
- u4Byte i;
-
- if(pDM_Odm->SupportICType == ODM_RTL8723A)
- {
- pDM_SWAT_Table->RSSI_cnt_A = 0;
- pDM_SWAT_Table->RSSI_cnt_B = 0;
- pDM_Odm->RSSI_test = FALSE;
- pDM_SWAT_Table->try_flag = 0xff;
- pDM_SWAT_Table->RSSI_Trying = 0;
- pDM_SWAT_Table->SelectAntennaMap=0xAA;
-
- }
- else if(pDM_Odm->SupportICType & (ODM_RTL8723B|ODM_RTL8821))
- {
- pDM_Odm->RSSI_test = FALSE;
- pDM_SWAT_Table->try_flag = 0xff;
- pDM_SWAT_Table->RSSI_Trying = 0;
- pDM_SWAT_Table->Double_chk_flag= 0;
-
- pDM_FatTable->RxIdleAnt=MAIN_ANT;
-
- for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)
- {
- pDM_FatTable->MainAnt_Sum[i] = 0;
- pDM_FatTable->AuxAnt_Sum[i] = 0;
- pDM_FatTable->MainAnt_Cnt[i] = 0;
- pDM_FatTable->AuxAnt_Cnt[i] = 0;
- }
-
- }
-}
-\r
-\r
-#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))\r
VOID\r
-odm_AntDiv_on_off( IN PDM_ODM_T pDM_Odm ,IN u1Byte swch)\r
+ODM_SwAntDivRestAfterLink(\r
+ IN PVOID pDM_VOID\r
+ )\r
{\r
- if(pDM_Odm->AntDivType==S0S1_SW_ANTDIV || pDM_Odm->AntDivType==CGCS_RX_SW_ANTDIV) \r
- return;\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;\r
+ pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;\r
+ u4Byte i;\r
\r
- if(pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT)\r
+ if(pDM_Odm->SupportICType == ODM_RTL8723A)\r
{\r
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("(( Turn %s )) N-Series HW-AntDiv block\n",(swch==ANTDIV_ON)?"ON" : "OFF"));\r
- ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, swch); //OFDM AntDiv function block enable\r
- if( pDM_Odm->AntDivType != S0S1_SW_ANTDIV)\r
- ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, swch); //CCK AntDiv function block enable\r
+ pDM_SWAT_Table->RSSI_cnt_A = 0;\r
+ pDM_SWAT_Table->RSSI_cnt_B = 0;\r
+ pDM_Odm->RSSI_test = FALSE;\r
+ pDM_SWAT_Table->try_flag = 0xff;\r
+ pDM_SWAT_Table->RSSI_Trying = 0;\r
+ pDM_SWAT_Table->SelectAntennaMap=0xAA;\r
+ \r
+ }\r
+ else if(pDM_Odm->SupportICType & (ODM_RTL8723B|ODM_RTL8821))\r
+ {\r
+ pDM_Odm->RSSI_test = FALSE;\r
+ pDM_SWAT_Table->try_flag = 0xff;\r
+ pDM_SWAT_Table->RSSI_Trying = 0;\r
+ pDM_SWAT_Table->Double_chk_flag= 0;\r
+ \r
+ pDM_FatTable->RxIdleAnt=MAIN_ANT;\r
+ \r
+ for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)\r
+ {\r
+ pDM_FatTable->MainAnt_Sum[i] = 0;\r
+ pDM_FatTable->AuxAnt_Sum[i] = 0;\r
+ pDM_FatTable->MainAnt_Cnt[i] = 0;\r
+ pDM_FatTable->AuxAnt_Cnt[i] = 0;\r
+ }\r
+\r
}\r
- else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT)\r
+}\r
+\r
+\r
+#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))\r
+VOID\r
+odm_AntDiv_on_off( \r
+ IN PVOID pDM_VOID ,\r
+ IN u1Byte swch\r
+ )\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;\r
+ \r
+ if(pDM_FatTable->AntDiv_OnOff != swch)\r
{\r
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("(( Turn %s )) AC-Series HW-AntDiv block\n",(swch==ANTDIV_ON)?"ON" : "OFF"));\r
- if(pDM_Odm->SupportICType == ODM_RTL8812)\r
+ if(pDM_Odm->AntDivType==S0S1_SW_ANTDIV || pDM_Odm->AntDivType==CGCS_RX_SW_ANTDIV) \r
+ return;\r
+\r
+ if(pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT)\r
{\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("(( Turn %s )) N-Series HW-AntDiv block\n",(swch==ANTDIV_ON)?"ON" : "OFF"));\r
ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, swch); //OFDM AntDiv function block enable\r
- //ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, swch); //CCK AntDiv function block enable\r
+ ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, swch); //CCK AntDiv function block enable\r
}\r
- else\r
+ else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT)\r
{\r
- ODM_SetBBReg(pDM_Odm, 0x8D4 , BIT24, swch); //OFDM AntDiv function block enable\r
- \r
- if( (pDM_Odm->CutVersion >= ODM_CUT_C) && (pDM_Odm->SupportICType == ODM_RTL8821) && ( pDM_Odm->AntDivType != S0S1_SW_ANTDIV))\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("(( Turn %s )) AC-Series HW-AntDiv block\n",(swch==ANTDIV_ON)?"ON" : "OFF"));\r
+ if(pDM_Odm->SupportICType == ODM_RTL8812)\r
{\r
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("(( Turn %s )) CCK HW-AntDiv block\n",(swch==ANTDIV_ON)?"ON" : "OFF"));\r
- ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, swch); \r
- ODM_SetBBReg(pDM_Odm, 0xA00 , BIT15, swch); //CCK AntDiv function block enable\r
+ ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, swch); //OFDM AntDiv function block enable\r
+ ODM_SetBBReg(pDM_Odm, 0xa00 , BIT15, swch); //CCK AntDiv function block enable\r
}\r
- }\r
- }\r
+ else\r
+ {\r
+ ODM_SetBBReg(pDM_Odm, 0x8D4 , BIT24, swch); //OFDM AntDiv function block enable\r
+ \r
+ if( (pDM_Odm->CutVersion >= ODM_CUT_C) && (pDM_Odm->SupportICType == ODM_RTL8821) && ( pDM_Odm->AntDivType != S0S1_SW_ANTDIV))\r
+ {\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("(( Turn %s )) CCK HW-AntDiv block\n",(swch==ANTDIV_ON)?"ON" : "OFF"));\r
+ ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, swch); \r
+ ODM_SetBBReg(pDM_Odm, 0xA00 , BIT15, swch); //CCK AntDiv function block enable\r
+ }\r
+ }\r
+ }\r
+ }\r
+ pDM_FatTable->AntDiv_OnOff =swch;\r
+ \r
+}\r
+\r
+VOID\r
+odm_FastTraining_enable(\r
+ IN PVOID pDM_VOID, \r
+ IN u1Byte swch\r
+ )\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ u1Byte enable;\r
+ \r
+ if( swch== FAT_ON)\r
+ enable=1;\r
+ else\r
+ enable=0;\r
+\r
+ if(pDM_Odm->SupportICType == ODM_RTL8188E)\r
+ {\r
+ \r
+ ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, enable); //enable fast training\r
+ }\r
+ else if(pDM_Odm->SupportICType == ODM_RTL8192E)\r
+ {\r
+ ODM_SetBBReg(pDM_Odm, 0xB34 , BIT28, enable); //enable fast training (path-A)\r
+ //ODM_SetBBReg(pDM_Odm, 0xB34 , BIT29, enable); //enable fast training (path-B)\r
+ }\r
+}\r
+\r
+VOID\r
+odm_Tx_By_TxDesc_or_Reg( \r
+ IN PVOID pDM_VOID, \r
+ IN u1Byte swch\r
+ )\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ u1Byte enable;\r
+ \r
+ if( swch== TX_BY_DESC)\r
+ enable=1;\r
+ else\r
+ enable=0;\r
+\r
+ if(pDM_Odm->AntDivType != CGCS_RX_HW_ANTDIV)\r
+ {\r
+ if(pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT)\r
+ {\r
+ ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, enable); \r
+ } \r
+ else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT)\r
+ {\r
+ ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, enable); \r
+ }\r
+ }\r
}\r
\r
VOID\r
-ODM_UpdateRxIdleAnt(IN PDM_ODM_T pDM_Odm, IN u1Byte Ant)\r
+ODM_UpdateRxIdleAnt(\r
+ IN PVOID pDM_VOID, \r
+ IN u1Byte Ant\r
+ )\r
{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;\r
u4Byte DefaultAnt, OptionalAnt,value32;\r
-\r
+ \r
//#if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))\r
//PADAPTER pAdapter = pDM_Odm->Adapter;\r
//HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] RxIdleAnt =%s\n",(Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));\r
\r
if(!(pDM_Odm->SupportICType & ODM_RTL8723B))\r
- pDM_FatTable->RxIdleAnt = Ant;\r
+ pDM_FatTable->RxIdleAnt = Ant;\r
\r
if(Ant == MAIN_ANT)\r
{\r
ODM_SetBBReg(pDM_Odm, 0xB38 , BIT8|BIT7|BIT6, OptionalAnt);//Optional RX\r
ODM_SetBBReg(pDM_Odm, 0x860, BIT14|BIT13|BIT12, DefaultAnt);//Default TX \r
}\r
+ #if (RTL8723B_SUPPORT == 1)\r
else if(pDM_Odm->SupportICType==ODM_RTL8723B)\r
{\r
value32 = ODM_GetBBReg(pDM_Odm, 0x948, 0xFFF);\r
- \r
- if (value32 !=0x280)\r
- ODM_UpdateRxIdleAnt_8723B(pDM_Odm, Ant, DefaultAnt, OptionalAnt);\r
- else\r
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: Fail to set RX antenna due to 0x948 = 0x280\n"));\r
+ \r
+ if(value32 !=0x280)\r
+ ODM_UpdateRxIdleAnt_8723B(pDM_Odm, Ant, DefaultAnt, OptionalAnt);\r
+ else\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Update Rx-Idle-Ant ] 8723B: Fail to set RX antenna due to 0x948 = 0x280\n"));\r
}\r
- else\r
+ #endif\r
+ else //88E\r
{\r
ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, DefaultAnt); //Default RX\r
ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, OptionalAnt); //Optional RX\r
- ODM_SetBBReg(pDM_Odm, 0x860, BIT14|BIT13|BIT12, DefaultAnt); //Default TX \r
- }\r
+ ODM_SetBBReg(pDM_Odm, 0x860, BIT14|BIT13|BIT12, DefaultAnt); //Default TX \r
+ }\r
}\r
else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT)\r
{\r
ODM_SetBBReg(pDM_Odm, ODM_REG_TRMUX_11AC , BIT27|BIT26|BIT25, DefaultAnt); //Default TX\r
*/\r
}\r
- \r
+\r
if(pDM_Odm->SupportICType==ODM_RTL8188E)\r
{ \r
ODM_SetMACReg(pDM_Odm, 0x6D8 , BIT7|BIT6, DefaultAnt); //\14PathA Resp Tx\r
{\r
ODM_SetMACReg(pDM_Odm, 0x6D8 , BIT10|BIT9|BIT8, DefaultAnt); //\14PathA Resp Tx\r
} \r
- \r
+\r
}\r
else// pDM_FatTable->RxIdleAnt == Ant\r
- {\r
+ {\r
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Stay in Ori-Ant ] RxIdleAnt =%s\n",(Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));\r
pDM_FatTable->RxIdleAnt = Ant;\r
}\r
\r
\r
VOID\r
-odm_UpdateTxAnt(IN PDM_ODM_T pDM_Odm, IN u1Byte Ant, IN u4Byte MacId)\r
+odm_UpdateTxAnt(\r
+ IN PVOID pDM_VOID, \r
+ IN u1Byte Ant, \r
+ IN u4Byte MacId\r
+ )\r
{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;\r
u1Byte TxAnt;\r
\r
- if(Ant == MAIN_ANT)\r
- TxAnt = ANT1_2G;\r
+ if (pDM_Odm->AntDivType==CG_TRX_SMART_ANTDIV)\r
+ {\r
+ TxAnt=Ant;\r
+ }\r
else\r
- TxAnt = ANT2_2G;\r
+ {\r
+ if(Ant == MAIN_ANT)\r
+ TxAnt = ANT1_2G;\r
+ else\r
+ TxAnt = ANT2_2G;\r
+ }\r
\r
pDM_FatTable->antsel_a[MacId] = TxAnt&BIT0;\r
pDM_FatTable->antsel_b[MacId] = (TxAnt&BIT1)>>1;\r
pDM_FatTable->antsel_c[MacId] = (TxAnt&BIT2)>>2;\r
- #if (DM_ODM_SUPPORT_TYPE == ODM_AP)\r
- if (pDM_Odm->antdiv_rssi)\r
- {\r
- //panic_printk("[Tx from TxInfo]: MacID:(( %d )), TxAnt = (( %s ))\n",MacId,(Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT");\r
- //panic_printk("antsel_tr_mux=(( 3'b%d%d%d ))\n", pDM_FatTable->antsel_c[MacId] , pDM_FatTable->antsel_b[MacId] , pDM_FatTable->antsel_a[MacId] );\r
+ \r
+ //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Tx from TxInfo]: MacID:(( %d )), TxAnt = (( %s ))\n", MacId,(Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));\r
+ //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("antsel_tr_mux=(( 3'b%d%d%d ))\n",pDM_FatTable->antsel_c[MacId] , pDM_FatTable->antsel_b[MacId] , pDM_FatTable->antsel_a[MacId] ));\r
+ \r
+}\r
+\r
+#ifdef BEAMFORMING_SUPPORT\r
+#if(DM_ODM_SUPPORT_TYPE == ODM_AP)\r
+\r
+VOID\r
+odm_BDC_Init(\r
+ IN PVOID pDM_VOID\r
+ )\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ pBDC_T pDM_BdcTable=&pDM_Odm->DM_BdcTable;\r
+\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n[ BDC Initialization......] \n"));\r
+ pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE;\r
+ pDM_BdcTable->BDC_Mode=BDC_MODE_NULL;\r
+ pDM_BdcTable->BDC_Try_flag=0;\r
+ pDM_BdcTable->BDCcoexType_wBfer=0;\r
+ pDM_Odm->bdc_holdstate=0xff;\r
+ \r
+ if(pDM_Odm->SupportICType == ODM_RTL8192E)\r
+ {\r
+ ODM_SetBBReg(pDM_Odm, 0xd7c , 0x0FFFFFFF, 0x1081008); \r
+ ODM_SetBBReg(pDM_Odm, 0xd80 , 0x0FFFFFFF, 0); \r
+ }\r
+ else if(pDM_Odm->SupportICType == ODM_RTL8812)\r
+ {\r
+ ODM_SetBBReg(pDM_Odm, 0x9b0 , 0x0FFFFFFF, 0x1081008); //0x9b0[30:0] = 01081008\r
+ ODM_SetBBReg(pDM_Odm, 0x9b4 , 0x0FFFFFFF, 0); //0x9b4[31:0] = 00000000\r
+ }\r
+ \r
+}\r
+\r
+\r
+VOID\r
+odm_CSI_on_off(\r
+ IN PVOID pDM_VOID, \r
+ IN u1Byte CSI_en\r
+ )\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ if(CSI_en==CSI_ON)\r
+ {\r
+ if(pDM_Odm->SupportICType == ODM_RTL8192E)\r
+ {\r
+ ODM_SetMACReg(pDM_Odm, 0xd84 , BIT11, 1); //0xd84[11]=1\r
+ }\r
+ else if(pDM_Odm->SupportICType == ODM_RTL8812)\r
+ {\r
+ ODM_SetMACReg(pDM_Odm, 0x9b0 , BIT31, 1); //0x9b0[31]=1\r
+ }\r
+ \r
+ }\r
+ else if(CSI_en==CSI_OFF)\r
+ {\r
+ if(pDM_Odm->SupportICType == ODM_RTL8192E)\r
+ {\r
+ ODM_SetMACReg(pDM_Odm, 0xd84 , BIT11, 0); //0xd84[11]=0\r
+ }\r
+ else if(pDM_Odm->SupportICType == ODM_RTL8812)\r
+ {\r
+ ODM_SetMACReg(pDM_Odm, 0x9b0 , BIT31, 0); //0x9b0[31]=0\r
+ }\r
+ } \r
+}\r
+\r
+VOID\r
+odm_BDCcoexType_withBferClient(\r
+ IN PVOID pDM_VOID, \r
+ IN u1Byte swch\r
+ )\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ pBDC_T pDM_BdcTable = &pDM_Odm->DM_BdcTable;\r
+ u1Byte BDCcoexType_wBfer;\r
+ \r
+ if(swch==DIVON_CSIOFF)\r
+ {\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[BDCcoexType: 1] {DIV,CSI} ={1,0} \n"));\r
+ BDCcoexType_wBfer=1;\r
+\r
+ if(BDCcoexType_wBfer != pDM_BdcTable->BDCcoexType_wBfer)\r
+ {\r
+ odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON);\r
+ odm_CSI_on_off(pDM_Odm,CSI_OFF);\r
+ pDM_BdcTable->BDCcoexType_wBfer=1;\r
+ }\r
}\r
- #endif\r
- //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Tx from TxInfo]: MacID:(( %d )), TxAnt = (( %s ))\n", \r
- // MacId,(Ant==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));\r
- //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("antsel_tr_mux=(( 3'b%d%d%d ))\n",\r
- //pDM_FatTable->antsel_c[MacId] , pDM_FatTable->antsel_b[MacId] , pDM_FatTable->antsel_a[MacId] ));\r
+ else if(swch==DIVOFF_CSION)\r
+ {\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[BDCcoexType: 2] {DIV,CSI} ={0,1}\n"));\r
+ BDCcoexType_wBfer=2;\r
+\r
+ if(BDCcoexType_wBfer != pDM_BdcTable->BDCcoexType_wBfer)\r
+ {\r
+ odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);\r
+ odm_CSI_on_off(pDM_Odm,CSI_ON);\r
+ pDM_BdcTable->BDCcoexType_wBfer=2;\r
+ }\r
+ }\r
+}\r
+\r
+VOID\r
+odm_BF_AntDiv_ModeArbitration(\r
+ IN PVOID pDM_VOID\r
+ )\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ pBDC_T pDM_BdcTable = &pDM_Odm->DM_BdcTable;\r
+ u1Byte current_BDC_Mode;\r
+\r
+ #if(DM_ODM_SUPPORT_TYPE == ODM_AP)\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n"));\r
+ \r
+ //2 Mode 1\r
+ if((pDM_BdcTable->num_Txbfee_Client !=0) && (pDM_BdcTable->num_Txbfer_Client == 0))\r
+ {\r
+ current_BDC_Mode=BDC_MODE_1;\r
+ \r
+ if(current_BDC_Mode != pDM_BdcTable->BDC_Mode)\r
+ {\r
+ pDM_BdcTable->BDC_Mode=BDC_MODE_1;\r
+ odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF);\r
+ pDM_BdcTable->BDC_RxIdleUpdate_counter=1;\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to (( Mode1 ))\n"));\r
+ }\r
+\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Antdiv + BF coextance Mode] : (( Mode1 ))\n"));\r
+ }\r
+ //2 Mode 2\r
+ else if((pDM_BdcTable->num_Txbfee_Client ==0) && (pDM_BdcTable->num_Txbfer_Client != 0))\r
+ {\r
+ current_BDC_Mode=BDC_MODE_2;\r
+ \r
+ if(current_BDC_Mode != pDM_BdcTable->BDC_Mode)\r
+ {\r
+ pDM_BdcTable->BDC_Mode=BDC_MODE_2;\r
+ pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE;\r
+ pDM_BdcTable->BDC_Try_flag=0;\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to (( Mode2 ))\n"));\r
+ \r
+ }\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Antdiv + BF coextance Mode] : (( Mode2 ))\n"));\r
+ }\r
+ //2 Mode 3\r
+ else if((pDM_BdcTable->num_Txbfee_Client !=0) && (pDM_BdcTable->num_Txbfer_Client != 0))\r
+ {\r
+ current_BDC_Mode=BDC_MODE_3;\r
+ \r
+ if(current_BDC_Mode != pDM_BdcTable->BDC_Mode)\r
+ {\r
+ pDM_BdcTable->BDC_Mode=BDC_MODE_3;\r
+ pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE;\r
+ pDM_BdcTable->BDC_Try_flag=0;\r
+ pDM_BdcTable->BDC_RxIdleUpdate_counter=1;\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to (( Mode3 ))\n"));\r
+ }\r
+\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Antdiv + BF coextance Mode] : (( Mode3 ))\n"));\r
+ }\r
+ //2 Mode 4\r
+ else if((pDM_BdcTable->num_Txbfee_Client ==0) && (pDM_BdcTable->num_Txbfer_Client == 0))\r
+ {\r
+ current_BDC_Mode=BDC_MODE_4;\r
+ \r
+ if(current_BDC_Mode != pDM_BdcTable->BDC_Mode)\r
+ {\r
+ pDM_BdcTable->BDC_Mode=BDC_MODE_4;\r
+ odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF);\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to (( Mode4 ))\n"));\r
+ }\r
+\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Antdiv + BF coextance Mode] : (( Mode4 ))\n"));\r
+ }\r
+ #endif\r
+\r
+}\r
+\r
+VOID\r
+odm_DivTrainState_setting( \r
+ IN PVOID pDM_VOID\r
+ )\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ pBDC_T pDM_BdcTable=&pDM_Odm->DM_BdcTable;\r
+\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n*****[S T A R T ]***** [2-0. DIV_TRAIN_STATE] \n"));\r
+ pDM_BdcTable->BDC_Try_counter =2;\r
+ pDM_BdcTable->BDC_Try_flag=1; \r
+ pDM_BdcTable->BDC_state=BDC_BFer_TRAIN_STATE; \r
+ odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF);\r
+}\r
+\r
+VOID\r
+odm_BDCcoex_BFeeRxDiv_Arbitration(\r
+ IN PVOID pDM_VOID\r
+)\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ pBDC_T pDM_BdcTable = &pDM_Odm->DM_BdcTable;\r
+ BOOLEAN StopBF_flag;\r
+ u1Byte BDC_active_Mode;\r
+\r
+\r
+ #if(DM_ODM_SUPPORT_TYPE == ODM_AP)\r
+\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***{ num_BFee, num_BFer , num_Client} = (( %d , %d , %d)) \n",pDM_BdcTable->num_Txbfee_Client,pDM_BdcTable->num_Txbfer_Client,pDM_BdcTable->num_Client));\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***{ num_BF_tars, num_DIV_tars } = (( %d , %d )) \n",pDM_BdcTable->num_BfTar , pDM_BdcTable->num_DivTar ));\r
+\r
+ //2 [ MIB control ]\r
+ if (pDM_Odm->bdc_holdstate==2) \r
+ {\r
+ odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION); \r
+ pDM_BdcTable->BDC_state=BDC_BF_HOLD_STATE;\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Force in [ BF STATE] \n"));\r
+ return; \r
+ }\r
+ else if (pDM_Odm->bdc_holdstate==1) \r
+ {\r
+ pDM_BdcTable->BDC_state=BDC_DIV_HOLD_STATE;\r
+ odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF); \r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Force in [ DIV STATE] \n"));\r
+ return; \r
+ }\r
+\r
+ //------------------------------------------------------------\r
+\r
+\r
+ \r
+ //2 Mode 2 & 3\r
+ if(pDM_BdcTable->BDC_Mode==BDC_MODE_2 ||pDM_BdcTable->BDC_Mode==BDC_MODE_3)\r
+ {\r
+\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n{ Try_flag , Try_counter } = { %d , %d } \n",pDM_BdcTable->BDC_Try_flag,pDM_BdcTable->BDC_Try_counter));\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BDCcoexType = (( %d )) \n\n", pDM_BdcTable->BDCcoexType_wBfer));\r
+ \r
+ // All Client have Bfer-Cap-------------------------------\r
+ if(pDM_BdcTable->num_Txbfer_Client == pDM_BdcTable->num_Client) //BFer STA Only?: yes\r
+ {\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BFer STA only? (( Yes ))\n"));\r
+ pDM_BdcTable->BDC_Try_flag=0;\r
+ pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE;\r
+ odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION);\r
+ return;\r
+ }\r
+ else\r
+ {\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BFer STA only? (( No ))\n"));\r
+ }\r
+ //\r
+ if(pDM_BdcTable->bAll_BFSta_Idle==FALSE && pDM_BdcTable->bAll_DivSta_Idle==TRUE)\r
+ {\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("All DIV-STA are idle, but BF-STA not\n"));\r
+ pDM_BdcTable->BDC_Try_flag=0;\r
+ pDM_BdcTable->BDC_state=BDC_BFer_TRAIN_STATE;\r
+ odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION);\r
+ return;\r
+ }\r
+ else if(pDM_BdcTable->bAll_BFSta_Idle==TRUE && pDM_BdcTable->bAll_DivSta_Idle==FALSE)\r
+ {\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("All BF-STA are idle, but DIV-STA not\n"));\r
+ pDM_BdcTable->BDC_Try_flag=0;\r
+ pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE;\r
+ odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF);\r
+ return;\r
+ }\r
+\r
+ //Select active mode--------------------------------------\r
+ if(pDM_BdcTable->num_BfTar ==0) // Selsect_1, Selsect_2\r
+ {\r
+ if(pDM_BdcTable->num_DivTar ==0) // Selsect_3\r
+ {\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Select active mode (( 1 )) \n"));\r
+ pDM_BdcTable->BDC_active_Mode=1;\r
+ }\r
+ else\r
+ {\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Select active mode (( 2 ))\n"));\r
+ pDM_BdcTable->BDC_active_Mode=2;\r
+ }\r
+ pDM_BdcTable->BDC_Try_flag=0;\r
+ pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE;\r
+ odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF);\r
+ return;\r
+ }\r
+ else // num_BfTar > 0\r
+ { \r
+ if(pDM_BdcTable->num_DivTar ==0) // Selsect_3\r
+ {\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Select active mode (( 3 ))\n")); \r
+ pDM_BdcTable->BDC_active_Mode=3;\r
+ pDM_BdcTable->BDC_Try_flag=0;\r
+ pDM_BdcTable->BDC_state=BDC_BFer_TRAIN_STATE;\r
+ odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION);\r
+ return;\r
+ }\r
+ else // Selsect_4\r
+ {\r
+ BDC_active_Mode=4;\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Select active mode (( 4 ))\n")); \r
+ \r
+ if(BDC_active_Mode!=pDM_BdcTable->BDC_active_Mode)\r
+ {\r
+ pDM_BdcTable->BDC_active_Mode=4;\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Change to active mode (( 4 )) & return!!! \n")); \r
+ return;\r
+ }\r
+ }\r
+ }\r
+\r
+#if 1\r
+ if (pDM_Odm->bdc_holdstate==0xff) \r
+ {\r
+ pDM_BdcTable->BDC_state=BDC_DIV_HOLD_STATE;\r
+ odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF); \r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Force in [ DIV STATE] \n")); \r
+ return;\r
+ }\r
+#endif\r
+\r
+ // Does Client number changed ? -------------------------------\r
+ if(pDM_BdcTable->num_Client !=pDM_BdcTable->pre_num_Client)\r
+ { \r
+ pDM_BdcTable->BDC_Try_flag=0;\r
+ pDM_BdcTable->BDC_state=BDC_DIV_TRAIN_STATE;\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ The number of client has been changed !!!] return to (( BDC_DIV_TRAIN_STATE )) \n")); \r
+ }\r
+ pDM_BdcTable->pre_num_Client=pDM_BdcTable->num_Client;\r
+\r
+ if( pDM_BdcTable->BDC_Try_flag==0)\r
+ {\r
+ //2 DIV_TRAIN_STATE (Mode 2-0)\r
+ if(pDM_BdcTable->BDC_state==BDC_DIV_TRAIN_STATE)\r
+ {\r
+ odm_DivTrainState_setting( pDM_Odm);\r
+ }\r
+ //2 BFer_TRAIN_STATE (Mode 2-1)\r
+ else if(pDM_BdcTable->BDC_state==BDC_BFer_TRAIN_STATE) \r
+ {\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*****[2-1. BFer_TRAIN_STATE ]***** \n"));\r
+ \r
+ //if(pDM_BdcTable->num_BfTar==0) \r
+ //{\r
+ // ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( No )), [ BDC_BFer_TRAIN_STATE ] >> [BDC_DIV_TRAIN_STATE] \n"));\r
+ // odm_DivTrainState_setting( pDM_Odm);\r
+ //}\r
+ //else //num_BfTar != 0\r
+ //{\r
+ pDM_BdcTable->BDC_Try_counter=2;\r
+ pDM_BdcTable->BDC_Try_flag=1;\r
+ pDM_BdcTable->BDC_state=BDC_DECISION_STATE;\r
+ odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION); \r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( Yes )), [ BDC_BFer_TRAIN_STATE ] >> [BDC_DECISION_STATE] \n"));\r
+ //}\r
+ }\r
+ //2 DECISION_STATE (Mode 2-2)\r
+ else if(pDM_BdcTable->BDC_state==BDC_DECISION_STATE)\r
+ { \r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*****[2-2. DECISION_STATE]***** \n"));\r
+ //if(pDM_BdcTable->num_BfTar==0) \r
+ //{\r
+ // ODM_AntDiv_Printk(("BF_tars exist? : (( No )), [ DECISION_STATE ] >> [BDC_DIV_TRAIN_STATE] \n"));\r
+ // odm_DivTrainState_setting( pDM_Odm);\r
+ //}\r
+ //else //num_BfTar != 0\r
+ //{\r
+ if(pDM_BdcTable->BF_pass==FALSE || pDM_BdcTable->DIV_pass == FALSE)\r
+ StopBF_flag=TRUE;\r
+ else\r
+ StopBF_flag=FALSE;\r
+ \r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( Yes )), {BF_pass, DIV_pass, StopBF_flag } = { %d, %d, %d } \n" ,pDM_BdcTable->BF_pass,pDM_BdcTable->DIV_pass,StopBF_flag));\r
+ \r
+ if(StopBF_flag==TRUE) //DIV_en\r
+ {\r
+ pDM_BdcTable->BDC_Hold_counter=10; //20\r
+ odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF); \r
+ pDM_BdcTable->BDC_state=BDC_DIV_HOLD_STATE;\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ StopBF_flag= ((TRUE)), BDC_DECISION_STATE ] >> [BDC_DIV_HOLD_STATE] \n"));\r
+ }\r
+ else //BF_en\r
+ {\r
+ pDM_BdcTable->BDC_Hold_counter=10; //20\r
+ odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION); \r
+ pDM_BdcTable->BDC_state=BDC_BF_HOLD_STATE;\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[StopBF_flag= ((FALSE)), BDC_DECISION_STATE ] >> [BDC_BF_HOLD_STATE] \n"));\r
+ }\r
+ //}\r
+ }\r
+ //2 BF-HOLD_STATE (Mode 2-3)\r
+ else if(pDM_BdcTable->BDC_state==BDC_BF_HOLD_STATE)\r
+ {\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*****[2-3. BF_HOLD_STATE ]*****\n")); \r
+\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BDC_Hold_counter = (( %d )) \n",pDM_BdcTable->BDC_Hold_counter )); \r
+\r
+ if(pDM_BdcTable->BDC_Hold_counter==1)\r
+ {\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE] \n")); \r
+ odm_DivTrainState_setting( pDM_Odm);\r
+ }\r
+ else\r
+ {\r
+ pDM_BdcTable->BDC_Hold_counter--;\r
+ \r
+ //if(pDM_BdcTable->num_BfTar==0) \r
+ //{\r
+ // ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( No )), [ BDC_BF_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE] \n")); \r
+ // odm_DivTrainState_setting( pDM_Odm);\r
+ //}\r
+ //else //num_BfTar != 0\r
+ //{\r
+ //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BF_tars exist? : (( Yes ))\n")); \r
+ pDM_BdcTable->BDC_state=BDC_BF_HOLD_STATE;\r
+ odm_BDCcoexType_withBferClient( pDM_Odm, DIVOFF_CSION);\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ BDC_BF_HOLD_STATE ] >> [BDC_BF_HOLD_STATE] \n")); \r
+ //}\r
+ }\r
+ \r
+ }\r
+ //2 DIV-HOLD_STATE (Mode 2-4)\r
+ else if(pDM_BdcTable->BDC_state==BDC_DIV_HOLD_STATE)\r
+ {\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*****[2-4. DIV_HOLD_STATE ]*****\n")); \r
+ \r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("BDC_Hold_counter = (( %d )) \n",pDM_BdcTable->BDC_Hold_counter ));\r
+ \r
+ if(pDM_BdcTable->BDC_Hold_counter==1)\r
+ {\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_TRAIN_STATE] \n")); \r
+ odm_DivTrainState_setting( pDM_Odm);\r
+ }\r
+ else\r
+ {\r
+ pDM_BdcTable->BDC_Hold_counter--;\r
+ pDM_BdcTable->BDC_state=BDC_DIV_HOLD_STATE;\r
+ odm_BDCcoexType_withBferClient( pDM_Odm, DIVON_CSIOFF); \r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ BDC_DIV_HOLD_STATE ] >> [BDC_DIV_HOLD_STATE] \n")); \r
+ }\r
+ \r
+ }\r
+ \r
+ }\r
+ else if( pDM_BdcTable->BDC_Try_flag==1)\r
+ {\r
+ //2 Set Training Counter\r
+ if(pDM_BdcTable->BDC_Try_counter >1)\r
+ {\r
+ pDM_BdcTable->BDC_Try_counter--;\r
+ if(pDM_BdcTable->BDC_Try_counter ==1)\r
+ pDM_BdcTable->BDC_Try_flag=0; \r
+ \r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Training !!\n"));\r
+ //return ;\r
+ }\r
+ \r
+ }\r
+ \r
+ }\r
+\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n[end]\n"));\r
+\r
+ #endif //#if(DM_ODM_SUPPORT_TYPE == ODM_AP)\r
+\r
+\r
+\r
+\r
\r
+\r
}\r
\r
+#endif\r
+#endif //#ifdef BEAMFORMING_SUPPORT\r
\r
\r
#if (RTL8188E_SUPPORT == 1)\r
\r
VOID\r
odm_RX_HWAntDiv_Init_88E(\r
- IN PDM_ODM_T pDM_Odm\r
+ IN PVOID pDM_VOID\r
)\r
{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
u4Byte value32;\r
\r
- pDM_Odm->AntType = ODM_AUTO_ANT;\r
-\r
if(pDM_Odm->mp_mode == TRUE)\r
{\r
- pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;\r
- ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv \r
- ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); // 1:CG, 0:CS\r
+ pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv \r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_LNA_SWITCH_11N , BIT31, 1); // 1:CG, 0:CS\r
return;\r
}\r
\r
\r
VOID\r
odm_TRX_HWAntDiv_Init_88E(\r
- IN PDM_ODM_T pDM_Odm\r
+ IN PVOID pDM_VOID\r
)\r
{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
u4Byte value32;\r
\r
if(pDM_Odm->mp_mode == TRUE)\r
{\r
- pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;\r
- ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv \r
- ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, 0); //Default RX (0/1)\r
- return;\r
+ pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_IGI_A_11N , BIT7, 0); // disable HW AntDiv \r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_RX_ANT_CTRL_11N , BIT5|BIT4|BIT3, 0); //Default RX (0/1)\r
+ return;\r
}\r
\r
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init => AntDivType=[CG_TRX_HW_ANTDIV (SPDT)]\n"));\r
ODM_SetBBReg(pDM_Odm, ODM_REG_RX_DEFUALT_A_11N , BIT13|BIT12|BIT11, 2); //Reg858[13:11]=3'b010\r
}\r
else //MPchip\r
- ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , bMaskDWord, 0x0001); //Reg914=3'b010, Reg915=3'b001\r
+ ODM_SetBBReg(pDM_Odm, ODM_REG_ANT_MAPPING1_11N , bMaskDWord, 0x0201); /*Reg914=3'b010, Reg915=3'b001*/\r
}\r
\r
+\r
+#if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) )\r
VOID\r
odm_Smart_HWAntDiv_Init_88E(\r
- IN PDM_ODM_T pDM_Odm\r
+ IN PVOID pDM_VOID\r
)\r
{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
u4Byte value32, i;\r
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;\r
- u4Byte AntCombination = 2;\r
\r
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init => AntDivType=[CG_TRX_SMART_ANTDIV]\n"));\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init => AntDivType=[CG_TRX_SMART_ANTDIV]\n"));\r
\r
if(pDM_Odm->mp_mode == TRUE)\r
{\r
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("pDM_Odm->AntDivType: %d\n", pDM_Odm->AntDivType));\r
- return;\r
+ ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("pDM_Odm->AntDivType: %d\n", pDM_Odm->AntDivType));\r
+ return;\r
}\r
\r
+ pDM_FatTable->TrainIdx = 0;\r
+ pDM_FatTable->FAT_State = FAT_NORMAL_STATE;\r
+ \r
+ pDM_Odm->fat_comb_a=5;\r
+ pDM_Odm->antdiv_intvl = 0x64; // 100ms\r
+\r
for(i=0; i<6; i++)\r
{\r
pDM_FatTable->Bssid[i] = 0;\r
+ }\r
+ for(i=0; i< (pDM_Odm->fat_comb_a) ; i++)\r
+ {\r
pDM_FatTable->antSumRSSI[i] = 0;\r
pDM_FatTable->antRSSIcnt[i] = 0;\r
pDM_FatTable->antAveRSSI[i] = 0;\r
}\r
- pDM_FatTable->TrainIdx = 0;\r
- pDM_FatTable->FAT_State = FAT_NORMAL_STATE;\r
\r
//MAC Setting\r
value32 = ODM_GetMACReg(pDM_Odm, 0x4c, bMaskDWord);\r
ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0);//Reg870[8]=1'b0, Reg870[9]=1'b0 //antsel antselb by HW\r
ODM_SetBBReg(pDM_Odm, 0x864 , BIT10, 0); //Reg864[10]=1'b0 //antsel2 by HW\r
ODM_SetBBReg(pDM_Odm, 0xb2c , BIT22, 0); //Regb2c[22]=1'b0 //disable CS/CG switch\r
- ODM_SetBBReg(pDM_Odm, 0xb2c , BIT31, 1); //Regb2c[31]=1'b1 //output at CG only\r
+ ODM_SetBBReg(pDM_Odm, 0xb2c , BIT31, 0); //Regb2c[31]=1'b1 //output at CS only\r
ODM_SetBBReg(pDM_Odm, 0xca4 , bMaskDWord, 0x000000a0);\r
\r
//antenna mapping table\r
- if(AntCombination == 2)\r
+ if(pDM_Odm->fat_comb_a == 2)\r
{\r
if(!pDM_Odm->bIsMPChip) //testchip\r
{\r
ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 2);\r
}\r
}\r
- else if(AntCombination == 7)\r
+ else\r
{\r
if(!pDM_Odm->bIsMPChip) //testchip\r
{\r
}\r
else //MPchip\r
{\r
- ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 0);\r
- ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 1); \r
- ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte2, 2);\r
- ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte3, 3);\r
- ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte0, 4);\r
- ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte1, 5);\r
- ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte2, 6);\r
- ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte3, 7);\r
+ ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte0, 4); // 0: 3b'000\r
+ ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte1, 2); // 1: 3b'001 \r
+ ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte2, 0); // 2: 3b'010\r
+ ODM_SetBBReg(pDM_Odm, 0x914 , bMaskByte3, 1); // 3: 3b'011\r
+ ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte0, 3); // 4: 3b'100\r
+ ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte1, 5); // 5: 3b'101\r
+ ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte2, 6); // 6: 3b'110\r
+ ODM_SetBBReg(pDM_Odm, 0x918 , bMaskByte3, 255); // 7: 3b'111\r
}\r
}\r
\r
//Default Ant Setting when no fast training\r
- ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1); //Reg80c[21]=1'b1 //from TX Info\r
ODM_SetBBReg(pDM_Odm, 0x864 , BIT5|BIT4|BIT3, 0); //Default RX\r
ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, 1); //Optional RX\r
- //ODM_SetBBReg(pDM_Odm, 0x860 , BIT14|BIT13|BIT12, 1); //Default TX\r
+ ODM_SetBBReg(pDM_Odm, 0x860 , BIT14|BIT13|BIT12, 0);//Default TX\r
\r
//Enter Traing state\r
- ODM_SetBBReg(pDM_Odm, 0x864 , BIT2|BIT1|BIT0, (AntCombination-1)); //Reg864[2:0]=3'd6 //ant combination=reg864[2:0]+1\r
- //ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0); //RegC50[7]=1'b0 //disable HW AntDiv\r
- //ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 0); //RegE08[16]=1'b0 //disable fast training\r
- //ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 1); //RegE08[16]=1'b1 //enable fast training\r
- ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //RegC50[7]=1'b1 //enable HW AntDiv\r
+ ODM_SetBBReg(pDM_Odm, 0x864 , BIT2|BIT1|BIT0, (pDM_Odm->fat_comb_a-1)); //Reg864[2:0]=3'd6 //ant combination=reg864[2:0]+1\r
\r
//SW Control\r
//PHY_SetBBReg(Adapter, 0x864 , BIT10, 1);\r
//PHY_SetBBReg(Adapter, 0x860 , BIT9, 0);\r
//PHY_SetBBReg(Adapter, 0x860 , BIT8, 0);\r
}\r
+#endif\r
+\r
#endif //#if (RTL8188E_SUPPORT == 1)\r
\r
\r
#if (RTL8192E_SUPPORT == 1)\r
VOID\r
odm_RX_HWAntDiv_Init_92E(\r
- IN PDM_ODM_T pDM_Odm\r
+ IN PVOID pDM_VOID\r
)\r
{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;\r
\r
if(pDM_Odm->mp_mode == TRUE)\r
{\r
- //pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;\r
- odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);\r
- ODM_SetBBReg(pDM_Odm, 0xc50 , BIT8, 0); //r_rxdiv_enable_anta Regc50[8]=1'b0 0: control by c50[9]\r
- ODM_SetBBReg(pDM_Odm, 0xc50 , BIT9, 1); // 1:CG, 0:CS\r
- return;\r
+ //pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;\r
+ odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);\r
+ ODM_SetBBReg(pDM_Odm, 0xc50 , BIT8, 0); //r_rxdiv_enable_anta Regc50[8]=1'b0 0: control by c50[9]\r
+ ODM_SetBBReg(pDM_Odm, 0xc50 , BIT9, 1); // 1:CG, 0:CS\r
+ return;\r
}\r
\r
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8192E AntDiv_Init => AntDivType=[CGCS_RX_HW_ANTDIV]\n"));\r
\r
//CCK Settings\r
ODM_SetBBReg(pDM_Odm, 0xa04 , 0xF000000, 0); //Select which path to receive for CCK_1 & CCK_2\r
- ODM_SetBBReg(pDM_Odm, 0xb34 , BIT30, 1); //(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0\r
+ ODM_SetBBReg(pDM_Odm, 0xb34 , BIT30, 0); //(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0\r
ODM_SetBBReg(pDM_Odm, 0xa74 , BIT7, 1); //Fix CCK PHY status report issue\r
ODM_SetBBReg(pDM_Odm, 0xa0c , BIT4, 1); //CCK complete HW AntDiv within 64 samples \r
+ \r
+ #ifdef ODM_EVM_ENHANCE_ANTDIV\r
+ //EVM enhance AntDiv method init----------------------------------------------------------------------\r
+ pDM_FatTable->EVM_method_enable=0;\r
+ pDM_FatTable->FAT_State = NORMAL_STATE_MIAN;\r
+ pDM_Odm->antdiv_intvl = 0x64; \r
+ ODM_SetBBReg(pDM_Odm, 0x910 , 0x3f, 0xf ); \r
+ pDM_Odm->antdiv_evm_en=1;\r
+ //pDM_Odm->antdiv_period=1;\r
+\r
+ #endif\r
+ \r
}\r
\r
VOID\r
odm_TRX_HWAntDiv_Init_92E(\r
- IN PDM_ODM_T pDM_Odm\r
+ IN PVOID pDM_VOID\r
)\r
{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;\r
\r
if(pDM_Odm->mp_mode == TRUE)\r
{\r
- //pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;\r
- odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);\r
- ODM_SetBBReg(pDM_Odm, 0xc50 , BIT8, 0); //r_rxdiv_enable_anta Regc50[8]=1'b0 0: control by c50[9]\r
- ODM_SetBBReg(pDM_Odm, 0xc50 , BIT9, 1); // 1:CG, 0:CS\r
- return;\r
+ //pDM_Odm->AntDivType = CGCS_RX_SW_ANTDIV;\r
+ odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);\r
+ ODM_SetBBReg(pDM_Odm, 0xc50 , BIT8, 0); //r_rxdiv_enable_anta Regc50[8]=1'b0 0: control by c50[9]\r
+ ODM_SetBBReg(pDM_Odm, 0xc50 , BIT9, 1); // 1:CG, 0:CS\r
+ return;\r
}\r
\r
-#if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
- pDM_Odm->antdiv_rssi=0;\r
-#endif\r
-\r
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8192E AntDiv_Init => AntDivType=[CG_TRX_HW_ANTDIV]\n"));\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8192E AntDiv_Init => AntDivType=[ Only for DIR605, CG_TRX_HW_ANTDIV]\n"));\r
\r
//3 --RFE pin setting---------\r
//[MAC]\r
ODM_SetMACReg(pDM_Odm, 0x38, BIT11, 1); //DBG PAD Driving control (GPIO 8)\r
- ODM_SetMACReg(pDM_Odm, 0x4c, BIT23, 0); //path-A , RFE_CTRL_3 & RFE_CTRL_4\r
+ ODM_SetMACReg(pDM_Odm, 0x4c, BIT23, 0); //path-A , RFE_CTRL_3 \r
+ ODM_SetMACReg(pDM_Odm, 0x4c, BIT29, 1); //path-A , RFE_CTRL_8\r
//[BB]\r
- ODM_SetBBReg(pDM_Odm, 0x944 , BIT4|BIT3, 0x3); //RFE_buffer\r
+ ODM_SetBBReg(pDM_Odm, 0x944 , BIT3, 1); //RFE_buffer\r
+ ODM_SetBBReg(pDM_Odm, 0x944 , BIT8, 1); \r
ODM_SetBBReg(pDM_Odm, 0x940 , BIT7|BIT6, 0x0); // r_rfe_path_sel_ (RFE_CTRL_3)\r
- ODM_SetBBReg(pDM_Odm, 0x940 , BIT9|BIT8, 0x0); // r_rfe_path_sel_ (RFE_CTRL_4)\r
+ ODM_SetBBReg(pDM_Odm, 0x940 , BIT17|BIT16, 0x0); // r_rfe_path_sel_ (RFE_CTRL_8)\r
ODM_SetBBReg(pDM_Odm, 0x944 , BIT31, 0); //RFE_buffer\r
ODM_SetBBReg(pDM_Odm, 0x92C , BIT3, 0); //rfe_inv (RFE_CTRL_3)\r
- ODM_SetBBReg(pDM_Odm, 0x92C , BIT4, 1); //rfe_inv (RFE_CTRL_4)\r
- ODM_SetBBReg(pDM_Odm, 0x930 , 0xFF000, 0x88); //path-A , RFE_CTRL_3 & 4=> ANTSEL[0]\r
+ ODM_SetBBReg(pDM_Odm, 0x92C , BIT8, 1); //rfe_inv (RFE_CTRL_8)\r
+ ODM_SetBBReg(pDM_Odm, 0x930 , 0xF000, 0x8); //path-A , RFE_CTRL_3 \r
+ ODM_SetBBReg(pDM_Odm, 0x934 , 0xF, 0x8); //path-A , RFE_CTRL_8\r
//3 -------------------------\r
\r
//Pin Settings\r
ODM_SetBBReg(pDM_Odm, 0xC50 , BIT8, 0); //path-A //disable CS/CG switch\r
- ODM_SetBBReg(pDM_Odm, 0xC50 , BIT9, 1); //path-A //output at CG only\r
+\r
+/* Let it follows PHY_REG for bit9 setting\r
+ if(pDM_Odm->priv->pshare->rf_ft_var.use_ext_pa || pDM_Odm->priv->pshare->rf_ft_var.use_ext_lna)\r
+ ODM_SetBBReg(pDM_Odm, 0xC50 , BIT9, 1);//path-A //output at CS\r
+ else\r
+ ODM_SetBBReg(pDM_Odm, 0xC50 , BIT9, 0); //path-A //output at CG ->normal power\r
+*/\r
+\r
ODM_SetBBReg(pDM_Odm, 0x870 , BIT9|BIT8, 0); //path-A //antsel antselb by HW\r
ODM_SetBBReg(pDM_Odm, 0xB38 , BIT10, 0); //path-A //antsel2 by HW \r
\r
\r
//CCK Settings\r
ODM_SetBBReg(pDM_Odm, 0xa04 , 0xF000000, 0); //Select which path to receive for CCK_1 & CCK_2\r
- ODM_SetBBReg(pDM_Odm, 0xb34 , BIT30, 1); //(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0\r
+ ODM_SetBBReg(pDM_Odm, 0xb34 , BIT30, 0); //(92E) ANTSEL_CCK_opt = r_en_antsel_cck? ANTSEL_CCK: 1'b0\r
ODM_SetBBReg(pDM_Odm, 0xa74 , BIT7, 1); //Fix CCK PHY status report issue\r
ODM_SetBBReg(pDM_Odm, 0xa0c , BIT4, 1); //CCK complete HW AntDiv within 64 samples \r
\r
//Timming issue\r
ODM_SetBBReg(pDM_Odm, 0xE20 , BIT23|BIT22|BIT21|BIT20, 8); //keep antidx after tx for ACK ( unit x 32 mu sec)\r
+\r
+ #ifdef ODM_EVM_ENHANCE_ANTDIV\r
+ //EVM enhance AntDiv method init----------------------------------------------------------------------\r
+ pDM_FatTable->EVM_method_enable=0;\r
+ pDM_FatTable->FAT_State = NORMAL_STATE_MIAN;\r
+ pDM_Odm->antdiv_intvl = 0x64; \r
+ ODM_SetBBReg(pDM_Odm, 0x910 , 0x3f, 0xf ); \r
+ pDM_Odm->antdiv_evm_en=1;\r
+ //pDM_Odm->antdiv_period=1;\r
+ #endif\r
}\r
\r
+#if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) )\r
VOID\r
odm_Smart_HWAntDiv_Init_92E(\r
- IN PDM_ODM_T pDM_Odm\r
+ IN PVOID pDM_VOID\r
)\r
{\r
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init => AntDivType=[CG_TRX_SMART_ANTDIV]\n"));\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8188E AntDiv_Init => AntDivType=[CG_TRX_SMART_ANTDIV]\n"));\r
}\r
+#endif\r
+\r
#endif //#if (RTL8192E_SUPPORT == 1)\r
\r
\r
#if (RTL8723B_SUPPORT == 1)\r
VOID\r
odm_TRX_HWAntDiv_Init_8723B(\r
- IN PDM_ODM_T pDM_Odm\r
+ IN PVOID pDM_VOID\r
)\r
{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8723B AntDiv_Init => AntDivType=[CG_TRX_HW_ANTDIV(DPDT)]\n"));\r
\r
//Mapping Table\r
if(pDM_Odm->AntType == ODM_AUTO_ANT)\r
ODM_SetBBReg(pDM_Odm, 0xA00 , BIT15, 0); //CCK AntDiv function block enable\r
\r
- //ODM_SetBBReg(pDM_Odm, 0x80C , BIT21, 0); //TX Ant by Reg\r
-\r
-\r
}\r
\r
\r
\r
VOID\r
odm_S0S1_SWAntDiv_Init_8723B(\r
- IN PDM_ODM_T pDM_Odm\r
+ IN PVOID pDM_VOID\r
)\r
{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;\r
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;\r
\r
\r
VOID\r
odm_S0S1_SWAntDiv_Reset_8723B(\r
- IN PDM_ODM_T pDM_Odm\r
+ IN PVOID pDM_VOID\r
)\r
{\r
- pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;\r
- pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;\r
+ pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;\r
\r
pDM_FatTable->bBecomeLinked =FALSE;\r
pDM_SWAT_Table->try_flag = 0xff; \r
\r
VOID\r
ODM_UpdateRxIdleAnt_8723B(\r
- IN PDM_ODM_T pDM_Odm,\r
+ IN PVOID pDM_VOID,\r
IN u1Byte Ant,\r
IN u4Byte DefaultAnt, \r
IN u4Byte OptionalAnt\r
)\r
{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;\r
PADAPTER pAdapter = pDM_Odm->Adapter;\r
HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
#if (RTL8821A_SUPPORT == 1)\r
VOID\r
odm_TRX_HWAntDiv_Init_8821A(\r
- IN PDM_ODM_T pDM_Odm\r
-)\r
+ IN PVOID pDM_VOID\r
+ )\r
{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
\r
-#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) \r
-\r
- PADAPTER pAdapter = pDM_Odm->Adapter;\r
- pAdapter->HalFunc.GetHalDefVarHandler(pAdapter, HAL_DEF_5G_ANT_SELECT, (pu1Byte)(&pDM_Odm->AntType)); \r
-#else\r
- pDM_Odm->AntType = ODM_AUTO_ANT;\r
-#endif\r
- pAdapter->HalFunc.GetHalDefVarHandler(pAdapter, HAL_DEF_5G_ANT_SELECT, (pu1Byte)(&pDM_Odm->AntType)); \r
-\r
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821A AntDiv_Init => AntDivType=[ CG_TRX_HW_ANTDIV (DPDT)] \n"));\r
\r
//Output Pin Settings\r
ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte0, 0);\r
ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte1, 1);\r
\r
- //Set ANT1_8821A as MAIN_ANT\r
- if((pDM_Odm->AntType == ODM_FIX_MAIN_ANT) || (pDM_Odm->AntType == ODM_AUTO_ANT))\r
- ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);\r
- else\r
- ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT);\r
-\r
//OFDM HW AntDiv Parameters\r
ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF, 0xA0); //thershold\r
ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF000, 0x10); //bias\r
\r
//response TX ant by RX ant\r
ODM_SetMACReg(pDM_Odm, 0x668 , BIT3, 1);\r
- \r
-\r
\r
}\r
\r
VOID\r
odm_S0S1_SWAntDiv_Init_8821A(\r
- IN PDM_ODM_T pDM_Odm\r
-)\r
+ IN PVOID pDM_VOID\r
+ )\r
{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;\r
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;\r
\r
-\r
-\r
-#if (DM_ODM_SUPPORT_TYPE == ODM_WIN) \r
-\r
- PADAPTER pAdapter = pDM_Odm->Adapter;\r
- pAdapter->HalFunc.GetHalDefVarHandler(pAdapter, HAL_DEF_5G_ANT_SELECT, (pu1Byte)(&pDM_Odm->AntType)); \r
-#else\r
- pDM_Odm->AntType = ODM_AUTO_ANT;\r
-#endif\r
-\r
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8821A AntDiv_Init => AntDivType=[ S0S1_SW_AntDiv] \n"));\r
\r
//Output Pin Settings\r
ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte0, 0);\r
ODM_SetBBReg(pDM_Odm, 0xCA4 , bMaskByte1, 1);\r
\r
- //Set ANT1_8821A as MAIN_ANT\r
- if((pDM_Odm->AntType == ODM_FIX_MAIN_ANT) || (pDM_Odm->AntType == ODM_AUTO_ANT))\r
- ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);\r
- else\r
- ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT);\r
-\r
//OFDM HW AntDiv Parameters\r
ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF, 0xA0); //thershold\r
ODM_SetBBReg(pDM_Odm, 0x8D4 , 0x7FF000, 0x10); //bias\r
\r
//response TX ant by RX ant\r
ODM_SetMACReg(pDM_Odm, 0x668 , BIT3, 1);\r
- \r
- \r
+\r
+\r
ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 0); \r
\r
pDM_SWAT_Table->try_flag = 0xff; \r
#if (RTL8881A_SUPPORT == 1)\r
VOID\r
odm_RX_HWAntDiv_Init_8881A(\r
- IN PDM_ODM_T pDM_Odm\r
-)\r
+ IN PVOID pDM_VOID\r
+ )\r
{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8881A AntDiv_Init => AntDivType=[ CGCS_RX_HW_ANTDIV] \n"));\r
\r
}\r
\r
VOID\r
odm_TRX_HWAntDiv_Init_8881A(\r
- IN PDM_ODM_T pDM_Odm\r
-)\r
+ IN PVOID pDM_VOID\r
+ )\r
{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
\r
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8881A AntDiv_Init => AntDivType=[ CG_TRX_HW_ANTDIV (SPDT)] \n"));\r
\r
#if (RTL8812A_SUPPORT == 1)\r
VOID\r
odm_TRX_HWAntDiv_Init_8812A(\r
- IN PDM_ODM_T pDM_Odm\r
-)\r
+ IN PVOID pDM_VOID\r
+ )\r
{\r
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8812A AntDiv_Init => AntDivType=[ CG_TRX_HW_ANTDIV (SPDT)] \n"));\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***8812A AntDiv_Init => AntDivType=[ CG_TRX_HW_ANTDIV (SPDT)] \n"));\r
\r
//3 //3 --RFE pin setting---------\r
//[BB]\r
ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 0); //TX Ant by Reg // A-cut bug\r
\r
}\r
-\r
-#endif //#if (RTL8812A_SUPPORT == 1)\r
+\r
+#endif //#if (RTL8812A_SUPPORT == 1)\r
+\r
+\r
+\r
+\r
+#ifdef ODM_EVM_ENHANCE_ANTDIV\r
+\r
+\r
+\r
+VOID\r
+odm_EVM_FastAnt_Reset(\r
+ IN PVOID pDM_VOID\r
+ )\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;\r
+ \r
+ pDM_FatTable->EVM_method_enable=0;\r
+ odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON);\r
+ pDM_FatTable->FAT_State = NORMAL_STATE_MIAN;\r
+ pDM_Odm->antdiv_period=0;\r
+ ODM_SetMACReg(pDM_Odm, 0x608, BIT8, 0);\r
+}\r
+\r
+\r
+VOID\r
+odm_EVM_Enhance_AntDiv(\r
+ IN PVOID pDM_VOID\r
+ )\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ u4Byte Main_RSSI, Aux_RSSI ;\r
+ u4Byte Main_CRC_utility=0,Aux_CRC_utility=0,utility_ratio=1;\r
+ u4Byte Main_EVM, Aux_EVM,Diff_RSSI=0,diff_EVM=0; \r
+ u1Byte score_EVM=0,score_CRC=0;\r
+ pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;\r
+ u4Byte value32, i;\r
+ BOOLEAN Main_above1=FALSE,Aux_above1=FALSE;\r
+ BOOLEAN Force_antenna=FALSE;\r
+ PSTA_INFO_T pEntry;\r
+ pDM_FatTable->TargetAnt_enhance=0xFF;\r
+ \r
+ \r
+ if((pDM_Odm->SupportICType & ODM_EVM_ENHANCE_ANTDIV_SUPPORT_IC))\r
+ {\r
+ if(pDM_Odm->bOneEntryOnly)\r
+ {\r
+ //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[One Client only] \n"));\r
+ i = pDM_Odm->OneEntry_MACID;\r
+\r
+ Main_RSSI = (pDM_FatTable->MainAnt_Cnt[i]!=0)?(pDM_FatTable->MainAnt_Sum[i]/pDM_FatTable->MainAnt_Cnt[i]):0;\r
+ Aux_RSSI = (pDM_FatTable->AuxAnt_Cnt[i]!=0)?(pDM_FatTable->AuxAnt_Sum[i]/pDM_FatTable->AuxAnt_Cnt[i]):0;\r
+\r
+ if((Main_RSSI==0 && Aux_RSSI !=0 && Aux_RSSI>=FORCE_RSSI_DIFF) || (Main_RSSI!=0 && Aux_RSSI==0 && Main_RSSI>=FORCE_RSSI_DIFF))\r
+ {\r
+ Diff_RSSI=FORCE_RSSI_DIFF;\r
+ }\r
+ else if(Main_RSSI!=0 && Aux_RSSI !=0)\r
+ {\r
+ Diff_RSSI = (Main_RSSI>=Aux_RSSI)?(Main_RSSI-Aux_RSSI):(Aux_RSSI-Main_RSSI); \r
+ }\r
+ \r
+\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" Main_Cnt = (( %d )) , Main_RSSI= (( %d )) \n", pDM_FatTable->MainAnt_Cnt[i], Main_RSSI));\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" Aux_Cnt = (( %d )) , Aux_RSSI = (( %d )) \n" , pDM_FatTable->AuxAnt_Cnt[i] , Aux_RSSI));\r
+ \r
+ if( ((Main_RSSI>=Evm_RSSI_TH_High||Aux_RSSI>=Evm_RSSI_TH_High )|| (pDM_FatTable->EVM_method_enable==1) )\r
+ //&& (Diff_RSSI <= FORCE_RSSI_DIFF + 1)\r
+ )\r
+ {\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[> TH_H || EVM_method_enable==1] && "));\r
+ \r
+ if(((Main_RSSI>=Evm_RSSI_TH_Low)||(Aux_RSSI>=Evm_RSSI_TH_Low) ))\r
+ {\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[> TH_L ] \n"));\r
+\r
+ //2 [ Normal state Main]\r
+ if(pDM_FatTable->FAT_State == NORMAL_STATE_MIAN)\r
+ {\r
+\r
+ pDM_FatTable->EVM_method_enable=1;\r
+ odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);\r
+ pDM_Odm->antdiv_period=3;\r
+\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ start training: MIAN] \n"));\r
+ pDM_FatTable->MainAntEVM_Sum[i] = 0;\r
+ pDM_FatTable->AuxAntEVM_Sum[i] = 0;\r
+ pDM_FatTable->MainAntEVM_Cnt[i] = 0;\r
+ pDM_FatTable->AuxAntEVM_Cnt[i] = 0;\r
+\r
+ pDM_FatTable->FAT_State = NORMAL_STATE_AUX;\r
+ ODM_SetMACReg(pDM_Odm, 0x608, BIT8, 1); //Accept CRC32 Error packets.\r
+ ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);\r
+ \r
+ pDM_FatTable->CRC32_Ok_Cnt=0;\r
+ pDM_FatTable->CRC32_Fail_Cnt=0;\r
+ ODM_SetTimer(pDM_Odm,&pDM_Odm->EVM_FastAntTrainingTimer, pDM_Odm->antdiv_intvl ); //m\r
+ }\r
+ //2 [ Normal state Aux ]\r
+ else if(pDM_FatTable->FAT_State == NORMAL_STATE_AUX)\r
+ {\r
+ pDM_FatTable->MainCRC32_Ok_Cnt=pDM_FatTable->CRC32_Ok_Cnt;\r
+ pDM_FatTable->MainCRC32_Fail_Cnt=pDM_FatTable->CRC32_Fail_Cnt;\r
+ \r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ start training: AUX] \n"));\r
+ pDM_FatTable->FAT_State = TRAINING_STATE;\r
+ ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT);\r
+\r
+ pDM_FatTable->CRC32_Ok_Cnt=0;\r
+ pDM_FatTable->CRC32_Fail_Cnt=0;\r
+ ODM_SetTimer(pDM_Odm,&pDM_Odm->EVM_FastAntTrainingTimer, pDM_Odm->antdiv_intvl ); //ms\r
+ } \r
+ else if(pDM_FatTable->FAT_State == TRAINING_STATE)\r
+ {\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Training state ] \n"));\r
+ pDM_FatTable->FAT_State = NORMAL_STATE_MIAN;\r
+ \r
+ //3 [CRC32 statistic]\r
+ pDM_FatTable->AuxCRC32_Ok_Cnt=pDM_FatTable->CRC32_Ok_Cnt;\r
+ pDM_FatTable->AuxCRC32_Fail_Cnt=pDM_FatTable->CRC32_Fail_Cnt;\r
+\r
+ if( (pDM_FatTable->MainCRC32_Ok_Cnt >= ((pDM_FatTable->AuxCRC32_Ok_Cnt)<<1)) || (Diff_RSSI>=18))\r
+ {\r
+ pDM_FatTable->TargetAnt_CRC32=MAIN_ANT;\r
+ Force_antenna=TRUE;\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("CRC32 Force Main \n"));\r
+ }\r
+ else if((pDM_FatTable->AuxCRC32_Ok_Cnt >= ((pDM_FatTable->MainCRC32_Ok_Cnt)<<1)) || (Diff_RSSI>=18))\r
+ {\r
+ pDM_FatTable->TargetAnt_CRC32=AUX_ANT;\r
+ Force_antenna=TRUE;\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("CRC32 Force Aux \n"));\r
+ }\r
+ else\r
+ {\r
+ if(pDM_FatTable->MainCRC32_Fail_Cnt<=5)\r
+ pDM_FatTable->MainCRC32_Fail_Cnt=5;\r
+ \r
+ if(pDM_FatTable->AuxCRC32_Fail_Cnt<=5)\r
+ pDM_FatTable->AuxCRC32_Fail_Cnt=5;\r
+ \r
+ if(pDM_FatTable->MainCRC32_Ok_Cnt >pDM_FatTable->MainCRC32_Fail_Cnt )\r
+ Main_above1=TRUE;\r
+ \r
+ if(pDM_FatTable->AuxCRC32_Ok_Cnt >pDM_FatTable->AuxCRC32_Fail_Cnt )\r
+ Aux_above1=TRUE;\r
+\r
+ if(Main_above1==TRUE && Aux_above1==FALSE)\r
+ {\r
+ Force_antenna=TRUE;\r
+ pDM_FatTable->TargetAnt_CRC32=MAIN_ANT;\r
+ }\r
+ else if(Main_above1==FALSE && Aux_above1==TRUE)\r
+ {\r
+ Force_antenna=TRUE;\r
+ pDM_FatTable->TargetAnt_CRC32=AUX_ANT;\r
+ }\r
+ else if(Main_above1==TRUE && Aux_above1==TRUE)\r
+ {\r
+ Main_CRC_utility=((pDM_FatTable->MainCRC32_Ok_Cnt)<<7)/pDM_FatTable->MainCRC32_Fail_Cnt;\r
+ Aux_CRC_utility=((pDM_FatTable->AuxCRC32_Ok_Cnt)<<7)/pDM_FatTable->AuxCRC32_Fail_Cnt;\r
+ pDM_FatTable->TargetAnt_CRC32 = (Main_CRC_utility==Aux_CRC_utility)?(pDM_FatTable->pre_TargetAnt_enhance):((Main_CRC_utility>=Aux_CRC_utility)?MAIN_ANT:AUX_ANT);\r
+ \r
+ if(Main_CRC_utility!=0 && Aux_CRC_utility!=0)\r
+ {\r
+ if(Main_CRC_utility>=Aux_CRC_utility)\r
+ utility_ratio=(Main_CRC_utility<<1)/Aux_CRC_utility;\r
+ else\r
+ utility_ratio=(Aux_CRC_utility<<1)/Main_CRC_utility;\r
+ }\r
+ }\r
+ else if(Main_above1==FALSE && Aux_above1==FALSE)\r
+ {\r
+ if(pDM_FatTable->MainCRC32_Ok_Cnt==0)\r
+ pDM_FatTable->MainCRC32_Ok_Cnt=1;\r
+ if(pDM_FatTable->AuxCRC32_Ok_Cnt==0)\r
+ pDM_FatTable->AuxCRC32_Ok_Cnt=1;\r
+ \r
+ Main_CRC_utility=((pDM_FatTable->MainCRC32_Fail_Cnt)<<7)/pDM_FatTable->MainCRC32_Ok_Cnt;\r
+ Aux_CRC_utility=((pDM_FatTable->AuxCRC32_Fail_Cnt)<<7)/pDM_FatTable->AuxCRC32_Ok_Cnt;\r
+ pDM_FatTable->TargetAnt_CRC32 = (Main_CRC_utility==Aux_CRC_utility)?(pDM_FatTable->pre_TargetAnt_enhance):((Main_CRC_utility<=Aux_CRC_utility)?MAIN_ANT:AUX_ANT); \r
+\r
+ if(Main_CRC_utility!=0 && Aux_CRC_utility!=0)\r
+ {\r
+ if(Main_CRC_utility>=Aux_CRC_utility)\r
+ utility_ratio=(Main_CRC_utility<<1)/(Aux_CRC_utility);\r
+ else\r
+ utility_ratio=(Aux_CRC_utility<<1)/(Main_CRC_utility);\r
+ }\r
+ }\r
+ }\r
+ ODM_SetMACReg(pDM_Odm, 0x608, BIT8, 0);//NOT Accept CRC32 Error packets.\r
+\r
+ //3 [EVM statistic] \r
+ Main_EVM = (pDM_FatTable->MainAntEVM_Cnt[i]!=0)?(pDM_FatTable->MainAntEVM_Sum[i]/pDM_FatTable->MainAntEVM_Cnt[i]):0;\r
+ Aux_EVM = (pDM_FatTable->AuxAntEVM_Cnt[i]!=0)?(pDM_FatTable->AuxAntEVM_Sum[i]/pDM_FatTable->AuxAntEVM_Cnt[i]):0;\r
+ pDM_FatTable->TargetAnt_EVM = (Main_EVM==Aux_EVM)?(pDM_FatTable->pre_TargetAnt_enhance):((Main_EVM>=Aux_EVM)?MAIN_ANT:AUX_ANT);\r
+\r
+ if((Main_EVM==0 || Aux_EVM==0))\r
+ diff_EVM=0;\r
+ else if(Main_EVM>=Aux_EVM)\r
+ diff_EVM=Main_EVM-Aux_EVM;\r
+ else\r
+ diff_EVM=Aux_EVM-Main_EVM;\r
+\r
+ //2 [ Decision state ] \r
+ if(pDM_FatTable->TargetAnt_EVM ==pDM_FatTable->TargetAnt_CRC32 )\r
+ {\r
+ if( (utility_ratio<2 && Force_antenna==FALSE) && diff_EVM<=2)\r
+ pDM_FatTable->TargetAnt_enhance=pDM_FatTable->pre_TargetAnt_enhance;\r
+ else\r
+ pDM_FatTable->TargetAnt_enhance=pDM_FatTable->TargetAnt_EVM;\r
+ }\r
+ else if(diff_EVM<=2 && (utility_ratio > 4 && Force_antenna==FALSE)) \r
+ {\r
+ pDM_FatTable->TargetAnt_enhance=pDM_FatTable->TargetAnt_CRC32;\r
+ }\r
+ else if(diff_EVM>=20) // \r
+ {\r
+ pDM_FatTable->TargetAnt_enhance=pDM_FatTable->TargetAnt_EVM;\r
+ }\r
+ else if(utility_ratio>=6 && Force_antenna==FALSE) // utility_ratio>3\r
+ {\r
+ pDM_FatTable->TargetAnt_enhance=pDM_FatTable->TargetAnt_CRC32;\r
+ }\r
+ else\r
+ {\r
+ if(Force_antenna==TRUE)\r
+ score_CRC=3;\r
+ else if(utility_ratio>=4) //>2\r
+ score_CRC=2;\r
+ else if(utility_ratio>=3) //>1.5\r
+ score_CRC=1;\r
+ else\r
+ score_CRC=0;\r
+ \r
+ if(diff_EVM>=10)\r
+ score_EVM=2;\r
+ else if(diff_EVM>=5)\r
+ score_EVM=1;\r
+ else\r
+ score_EVM=0;\r
+\r
+ if(score_CRC>score_EVM)\r
+ pDM_FatTable->TargetAnt_enhance=pDM_FatTable->TargetAnt_CRC32;\r
+ else if(score_CRC<score_EVM)\r
+ pDM_FatTable->TargetAnt_enhance=pDM_FatTable->TargetAnt_EVM;\r
+ else\r
+ pDM_FatTable->TargetAnt_enhance=pDM_FatTable->pre_TargetAnt_enhance;\r
+ }\r
+ pDM_FatTable->pre_TargetAnt_enhance=pDM_FatTable->TargetAnt_enhance;\r
+\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : MainEVM_Cnt = (( %d )) , Main_EVM= (( %d )) \n",i, pDM_FatTable->MainAntEVM_Cnt[i], Main_EVM));\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : AuxEVM_Cnt = (( %d )) , Aux_EVM = (( %d )) \n" ,i, pDM_FatTable->AuxAntEVM_Cnt[i] , Aux_EVM));\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** TargetAnt_EVM = (( %s ))\n", ( pDM_FatTable->TargetAnt_EVM ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("M_CRC_Ok = (( %d )) , M_CRC_Fail = (( %d )), Main_CRC_utility = (( %d )) \n" , pDM_FatTable->MainCRC32_Ok_Cnt, pDM_FatTable->MainCRC32_Fail_Cnt,Main_CRC_utility));\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("A_CRC_Ok = (( %d )) , A_CRC_Fail = (( %d )), Aux_CRC_utility = (( %d )) \n" , pDM_FatTable->AuxCRC32_Ok_Cnt, pDM_FatTable->AuxCRC32_Fail_Cnt,Aux_CRC_utility));\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** TargetAnt_CRC32 = (( %s ))\n", ( pDM_FatTable->TargetAnt_CRC32 ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("****** TargetAnt_enhance = (( %s ))******\n", ( pDM_FatTable->TargetAnt_enhance ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));\r
+ \r
+ \r
+ }\r
+ }\r
+ else // RSSI< = Evm_RSSI_TH_Low\r
+ { \r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ <TH_L: escape from > TH_L ] \n"));\r
+ odm_EVM_FastAnt_Reset(pDM_Odm);\r
+ }\r
+ }\r
+ else \r
+ { \r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[escape from> TH_H || EVM_method_enable==1] \n"));\r
+ odm_EVM_FastAnt_Reset(pDM_Odm);\r
+ }\r
+ }\r
+ else\r
+ {\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[multi-Client] \n"));\r
+ odm_EVM_FastAnt_Reset(pDM_Odm);\r
+ } \r
+ }\r
+}\r
+\r
+VOID\r
+odm_EVM_FastAntTrainingCallback(\r
+ IN PVOID pDM_VOID\r
+ )\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("******odm_EVM_FastAntTrainingCallback****** \n"));\r
+ odm_HW_AntDiv(pDM_Odm);\r
+}\r
+#endif\r
\r
VOID\r
odm_HW_AntDiv(\r
- IN PDM_ODM_T pDM_Odm\r
-)\r
+ IN PVOID pDM_VOID\r
+ )\r
{\r
- u4Byte i,MinMaxRSSI=0xFF, AntDivMaxRSSI=0, MaxRSSI=0, LocalMaxRSSI;\r
- u4Byte Main_RSSI, Aux_RSSI, pkt_ratio_m=0, pkt_ratio_a=0,pkt_threshold=10;\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ u4Byte i,MinMaxRSSI=0xFF, AntDivMaxRSSI=0, MaxRSSI=0, LocalMaxRSSI;\r
+ u4Byte Main_RSSI, Aux_RSSI;\r
u1Byte RxIdleAnt=0, TargetAnt=7;\r
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;\r
pDIG_T pDM_DigTable = &pDM_Odm->DM_DigTable;\r
PSTA_INFO_T pEntry;\r
\r
+ #ifdef BEAMFORMING_SUPPORT\r
+ #if(DM_ODM_SUPPORT_TYPE == ODM_AP)\r
+ pBDC_T pDM_BdcTable = &pDM_Odm->DM_BdcTable;\r
+ u4Byte TH1=500000;\r
+ u4Byte TH2=10000000; \r
+ u4Byte MA_rx_Temp, degrade_TP_temp, improve_TP_temp;\r
+ u1Byte Monitor_RSSI_threshold=30;\r
+\r
+ pDM_BdcTable->BF_pass=TRUE;\r
+ pDM_BdcTable->DIV_pass=TRUE;\r
+ pDM_BdcTable->bAll_DivSta_Idle=TRUE;\r
+ pDM_BdcTable->bAll_BFSta_Idle=TRUE;\r
+ pDM_BdcTable->num_BfTar=0 ;\r
+ pDM_BdcTable->num_DivTar=0;\r
+ pDM_BdcTable->num_Client=0;\r
+ #endif\r
+ #endif\r
+\r
if(!pDM_Odm->bLinked) //bLinked==False\r
{\r
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[No Link!!!]\n"));\r
- \r
- #if(DM_ODM_SUPPORT_TYPE == ODM_AP)\r
- if (pDM_Odm->antdiv_rssi)\r
- panic_printk("[No Link!!!]\n");\r
- #endif\r
- \r
+ \r
if(pDM_FatTable->bBecomeLinked == TRUE)\r
{\r
odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);\r
ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);\r
+ odm_Tx_By_TxDesc_or_Reg(pDM_Odm , REG);\r
+ pDM_Odm->antdiv_period=0;\r
\r
pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked;\r
}\r
{\r
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Linked !!!]\n"));\r
odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON);\r
+ odm_Tx_By_TxDesc_or_Reg(pDM_Odm , TX_BY_DESC);\r
+ \r
//if(pDM_Odm->SupportICType == ODM_RTL8821 )\r
//ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //CCK AntDiv function disable\r
\r
//#if(DM_ODM_SUPPORT_TYPE == ODM_AP)\r
- //else if(pDM_Odm->SupportICType == ODM_RTL8881 )\r
+ //else if(pDM_Odm->SupportICType == ODM_RTL8881A)\r
// ODM_SetBBReg(pDM_Odm, 0x800 , BIT25, 0); //CCK AntDiv function disable\r
//#endif\r
\r
ODM_SetBBReg(pDM_Odm, 0x930 , 0xF0, 8); // DPDT_P = ANTSEL[0] // for 8723B AntDiv function patch. BB Dino 130412 \r
ODM_SetBBReg(pDM_Odm, 0x930 , 0xF, 8); // DPDT_N = ANTSEL[0]\r
}\r
+ \r
+ //2 BDC Init\r
+ #ifdef BEAMFORMING_SUPPORT\r
+ #if(DM_ODM_SUPPORT_TYPE == ODM_AP)\r
+ odm_BDC_Init(pDM_Odm);\r
+ #endif\r
+ #endif\r
+ \r
+ #ifdef ODM_EVM_ENHANCE_ANTDIV\r
+ odm_EVM_FastAnt_Reset(pDM_Odm);\r
+ #endif\r
} \r
} \r
\r
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n[HW AntDiv] Start =>\n"));\r
- \r
+ //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("\n AntDiv Start =>\n"));\r
+\r
+ #ifdef ODM_EVM_ENHANCE_ANTDIV\r
+ if(pDM_Odm->antdiv_evm_en==1)\r
+ {\r
+ odm_EVM_Enhance_AntDiv(pDM_Odm);\r
+ if(pDM_FatTable->FAT_State !=NORMAL_STATE_MIAN)\r
+ return;\r
+ }\r
+ else\r
+ {\r
+ odm_EVM_FastAnt_Reset(pDM_Odm);\r
+ }\r
+ #endif\r
+ \r
+ //2 BDC Mode Arbitration\r
+ #ifdef BEAMFORMING_SUPPORT\r
+ #if(DM_ODM_SUPPORT_TYPE == ODM_AP)\r
+ if(pDM_Odm->antdiv_evm_en == 0 ||pDM_FatTable->EVM_method_enable==0)\r
+ {\r
+ odm_BF_AntDiv_ModeArbitration(pDM_Odm);\r
+ }\r
+ #endif\r
+ #endif\r
+\r
for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)\r
{\r
pEntry = pDM_Odm->pODM_StaInfo[i];\r
Main_RSSI = (pDM_FatTable->MainAnt_Cnt[i]!=0)?(pDM_FatTable->MainAnt_Sum[i]/pDM_FatTable->MainAnt_Cnt[i]):0;\r
Aux_RSSI = (pDM_FatTable->AuxAnt_Cnt[i]!=0)?(pDM_FatTable->AuxAnt_Sum[i]/pDM_FatTable->AuxAnt_Cnt[i]):0;\r
TargetAnt = (Main_RSSI==Aux_RSSI)?pDM_FatTable->RxIdleAnt:((Main_RSSI>=Aux_RSSI)?MAIN_ANT:AUX_ANT);\r
- /*\r
- if( pDM_FatTable->MainAnt_Cnt[i]!=0 && pDM_FatTable->AuxAnt_Cnt[i]!=0 )\r
- {\r
- pkt_ratio_m=( pDM_FatTable->MainAnt_Cnt[i] / pDM_FatTable->AuxAnt_Cnt[i] );\r
- pkt_ratio_a=( pDM_FatTable->AuxAnt_Cnt[i] / pDM_FatTable->MainAnt_Cnt[i] );\r
- \r
- if (pkt_ratio_m >= pkt_threshold)\r
- TargetAnt=MAIN_ANT;\r
- \r
- else if(pkt_ratio_a >= pkt_threshold)\r
- TargetAnt=AUX_ANT;\r
- }\r
- */ \r
- //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("*** SupportICType=[%lu] \n",pDM_Odm->SupportICType));\r
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Main_Cnt = (( %d )) , Main_RSSI= (( %d )) \n", pDM_FatTable->MainAnt_Cnt[i], Main_RSSI));\r
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Aux_Cnt = (( %d )) , Aux_RSSI = (( %d )) \n", pDM_FatTable->AuxAnt_Cnt[i] , Aux_RSSI ));\r
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** MAC ID:[ %d ] , TargetAnt = (( %s )) \n", i ,( TargetAnt ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));\r
-\r
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("*** Phy_AntSel_A=[ %d, %d, %d] \n",((pDM_Odm->DM_FatTable.antsel_rx_keep_0)&BIT2)>>2,\r
- ((pDM_Odm->DM_FatTable.antsel_rx_keep_0)&BIT1) >>1, ((pDM_Odm->DM_FatTable.antsel_rx_keep_0)&BIT0)));\r
- #if(DM_ODM_SUPPORT_TYPE == ODM_AP)\r
- if (pDM_Odm->antdiv_rssi)\r
- {\r
- panic_printk("*** SupportICType=[%lu] \n",pDM_Odm->SupportICType);\r
- //panic_printk("*** Phy_AntSel_A=[ %d, %d, %d] \n",((pDM_Odm->DM_FatTable.antsel_rx_keep_0)&BIT2)>>2,\r
- // ((pDM_Odm->DM_FatTable.antsel_rx_keep_0)&BIT1) >>1, ((pDM_Odm->DM_FatTable.antsel_rx_keep_0)&BIT0));\r
- //panic_printk("*** Phy_AntSel_B=[ %d, %d, %d] \n",((pDM_Odm->DM_FatTable.antsel_rx_keep_1)&BIT2)>>2,\r
- // ((pDM_Odm->DM_FatTable.antsel_rx_keep_1)&BIT1) >>1, ((pDM_Odm->DM_FatTable.antsel_rx_keep_1)&BIT0))\r
- panic_printk("*** Client[ %lu ] , Main_Cnt = (( %lu )) , Main_RSSI= (( %lu )) \n",i, pDM_FatTable->MainAnt_Cnt[i], Main_RSSI);\r
- panic_printk("*** Client[ %lu ] , Aux_Cnt = (( %lu )) , Aux_RSSI = (( %lu )) \n" ,i, pDM_FatTable->AuxAnt_Cnt[i] , Aux_RSSI);\r
- }\r
- #endif\r
-\r
+ \r
+ //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("*** SupportICType=[%d] \n",pDM_Odm->SupportICType));\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : Main_Cnt = (( %d )) , Main_RSSI= (( %d )) \n",i, pDM_FatTable->MainAnt_Cnt[i], Main_RSSI));\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : Aux_Cnt = (( %d )) , Aux_RSSI = (( %d )) \n" ,i, pDM_FatTable->AuxAnt_Cnt[i] , Aux_RSSI));\r
+ //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** MAC ID:[ %d ] , TargetAnt = (( %s )) \n", i ,( TargetAnt ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));\r
+ //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("*** Phy_AntSel_A=[ %d, %d, %d] \n",((pDM_Odm->DM_FatTable.antsel_rx_keep_0)&BIT2)>>2,\r
+ // ((pDM_Odm->DM_FatTable.antsel_rx_keep_0)&BIT1) >>1, ((pDM_Odm->DM_FatTable.antsel_rx_keep_0)&BIT0)));\r
\r
LocalMaxRSSI = (Main_RSSI>Aux_RSSI)?Main_RSSI:Aux_RSSI;\r
//2 Select MaxRSSI for DIG\r
RxIdleAnt = TargetAnt;\r
MinMaxRSSI = LocalMaxRSSI;\r
}\r
- /*\r
- if((pDM_FatTable->RxIdleAnt == MAIN_ANT) && (Main_RSSI == 0))\r
- Main_RSSI = Aux_RSSI;\r
- else if((pDM_FatTable->RxIdleAnt == AUX_ANT) && (Aux_RSSI == 0))\r
- Aux_RSSI = Main_RSSI;\r
- \r
- LocalMinRSSI = (Main_RSSI>Aux_RSSI)?Aux_RSSI:Main_RSSI;\r
- if(LocalMinRSSI < MinRSSI)\r
+\r
+ #ifdef ODM_EVM_ENHANCE_ANTDIV\r
+ if(pDM_Odm->antdiv_evm_en==1)\r
{\r
- MinRSSI = LocalMinRSSI;\r
- RxIdleAnt = TargetAnt;\r
- } \r
- */\r
+ if(pDM_FatTable->TargetAnt_enhance!=0xFF)\r
+ {\r
+ TargetAnt=pDM_FatTable->TargetAnt_enhance;\r
+ RxIdleAnt = pDM_FatTable->TargetAnt_enhance;\r
+ }\r
+ }\r
+ #endif\r
+\r
//2 Select TX Antenna\r
+ if(pDM_Odm->AntDivType != CGCS_RX_HW_ANTDIV)\r
+ {\r
+ #ifdef BEAMFORMING_SUPPORT\r
+ #if(DM_ODM_SUPPORT_TYPE == ODM_AP)\r
+ if(pDM_BdcTable->w_BFee_Client[i]==0)\r
+ #endif \r
+ #endif\r
+ {\r
+ odm_UpdateTxAnt(pDM_Odm, TargetAnt, i);\r
+ }\r
+ }\r
+\r
+ //------------------------------------------------------------\r
+\r
+ #ifdef BEAMFORMING_SUPPORT\r
+ #if(DM_ODM_SUPPORT_TYPE == ODM_AP) \r
+\r
+ pDM_BdcTable->num_Client++;\r
+\r
+ if(pDM_BdcTable->BDC_Mode==BDC_MODE_2 ||pDM_BdcTable->BDC_Mode==BDC_MODE_3)\r
+ {\r
+ //2 Byte Counter\r
+\r
+ MA_rx_Temp= (pEntry->rx_byte_cnt_LowMAW)<<3 ; // RX TP ( bit /sec)\r
+ \r
+ if(pDM_BdcTable->BDC_state==BDC_BFer_TRAIN_STATE)\r
+ {\r
+ pDM_BdcTable->MA_rx_TP_DIV[i]= MA_rx_Temp ;\r
+ }\r
+ else\r
+ {\r
+ pDM_BdcTable->MA_rx_TP[i] =MA_rx_Temp ;\r
+ }\r
+\r
+ if( (MA_rx_Temp < TH2) && (MA_rx_Temp > TH1) && (LocalMaxRSSI<=Monitor_RSSI_threshold))\r
+ {\r
+ if(pDM_BdcTable->w_BFer_Client[i]==1) // Bfer_Target\r
+ {\r
+ pDM_BdcTable->num_BfTar++;\r
+ \r
+ if(pDM_BdcTable->BDC_state==BDC_DECISION_STATE && pDM_BdcTable->BDC_Try_flag==0)\r
+ {\r
+ improve_TP_temp = (pDM_BdcTable->MA_rx_TP_DIV[i] * 9)>>3 ; //* 1.125\r
+ pDM_BdcTable->BF_pass = (pDM_BdcTable->MA_rx_TP[i] > improve_TP_temp)?TRUE:FALSE;\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : { MA_rx_TP,improve_TP_temp , MA_rx_TP_DIV, BF_pass}={ %d, %d, %d , %d } \n" ,i,pDM_BdcTable->MA_rx_TP[i],improve_TP_temp,pDM_BdcTable->MA_rx_TP_DIV[i], pDM_BdcTable->BF_pass ));\r
+ } \r
+ } \r
+ else// DIV_Target\r
+ {\r
+ pDM_BdcTable->num_DivTar++;\r
+ \r
+ if(pDM_BdcTable->BDC_state==BDC_DECISION_STATE && pDM_BdcTable->BDC_Try_flag==0)\r
+ {\r
+ degrade_TP_temp=(pDM_BdcTable->MA_rx_TP_DIV[i]*5)>>3;//* 0.625\r
+ pDM_BdcTable->DIV_pass = (pDM_BdcTable->MA_rx_TP[i] >degrade_TP_temp)?TRUE:FALSE;\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : { MA_rx_TP, degrade_TP_temp , MA_rx_TP_DIV, DIV_pass}=\n{ %d, %d, %d , %d } \n" ,i,pDM_BdcTable->MA_rx_TP[i],degrade_TP_temp,pDM_BdcTable->MA_rx_TP_DIV[i], pDM_BdcTable->DIV_pass ));\r
+ } \r
+ }\r
+ }\r
\r
- #if TX_BY_REG\r
+ if(MA_rx_Temp > TH1)\r
+ {\r
+ if(pDM_BdcTable->w_BFer_Client[i]==1) // Bfer_Target\r
+ {\r
+ pDM_BdcTable->bAll_BFSta_Idle=FALSE;\r
+ } \r
+ else// DIV_Target\r
+ {\r
+ pDM_BdcTable->bAll_DivSta_Idle=FALSE;\r
+ }\r
+ }\r
+ \r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : { BFmeeCap , BFmerCap} = { %d , %d } \n" ,i, pDM_BdcTable->w_BFee_Client[i] , pDM_BdcTable->w_BFer_Client[i]));\r
+\r
+ if(pDM_BdcTable->BDC_state==BDC_BFer_TRAIN_STATE)\r
+ {\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : MA_rx_TP_DIV = (( %d )) \n",i,pDM_BdcTable->MA_rx_TP_DIV[i] ));\r
+ \r
+ }\r
+ else\r
+ {\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** Client[ %d ] : MA_rx_TP = (( %d )) \n",i,pDM_BdcTable->MA_rx_TP[i] ));\r
+ }\r
\r
- #else\r
- if(pDM_Odm->AntDivType != CGCS_RX_HW_ANTDIV)\r
- odm_UpdateTxAnt(pDM_Odm, TargetAnt, i);\r
+ }\r
+ #endif\r
#endif\r
\r
}\r
- pDM_FatTable->MainAnt_Sum[i] = 0;\r
- pDM_FatTable->AuxAnt_Sum[i] = 0;\r
- pDM_FatTable->MainAnt_Cnt[i] = 0;\r
- pDM_FatTable->AuxAnt_Cnt[i] = 0;\r
+\r
+ #ifdef BEAMFORMING_SUPPORT\r
+ #if(DM_ODM_SUPPORT_TYPE == ODM_AP)\r
+ if(pDM_BdcTable->BDC_Try_flag==0)\r
+ #endif\r
+ #endif \r
+ {\r
+ pDM_FatTable->MainAnt_Sum[i] = 0;\r
+ pDM_FatTable->AuxAnt_Sum[i] = 0;\r
+ pDM_FatTable->MainAnt_Cnt[i] = 0;\r
+ pDM_FatTable->AuxAnt_Cnt[i] = 0;\r
+ }\r
}\r
\r
- //2 Set RX Idle Antenna\r
- ODM_UpdateRxIdleAnt(pDM_Odm, RxIdleAnt);\r
\r
- #if(DM_ODM_SUPPORT_TYPE == ODM_AP)\r
- if (pDM_Odm->antdiv_rssi)\r
- panic_printk("*** RxIdleAnt = (( %s )) \n \n", ( RxIdleAnt ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT");\r
- #endif\r
\r
+ //2 Set RX Idle Antenna & TX Antenna(Because of HW Bug ) \r
+ #if(DM_ODM_SUPPORT_TYPE == ODM_AP ) \r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** RxIdleAnt = (( %s ))\n\n", ( RxIdleAnt ==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));\r
+ \r
+ #ifdef BEAMFORMING_SUPPORT\r
+ #if(DM_ODM_SUPPORT_TYPE == ODM_AP)\r
+ if(pDM_BdcTable->BDC_Mode==BDC_MODE_1 ||pDM_BdcTable->BDC_Mode==BDC_MODE_3)\r
+ {\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** BDC_RxIdleUpdate_counter = (( %d ))\n", pDM_BdcTable->BDC_RxIdleUpdate_counter));\r
+ \r
+ if(pDM_BdcTable->BDC_RxIdleUpdate_counter==1)\r
+ {\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***Update RxIdle Antenna!!! \n"));\r
+ pDM_BdcTable->BDC_RxIdleUpdate_counter=30;\r
+ ODM_UpdateRxIdleAnt(pDM_Odm, RxIdleAnt);\r
+ }\r
+ else\r
+ {\r
+ pDM_BdcTable->BDC_RxIdleUpdate_counter--;\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***NOT update RxIdle Antenna because of BF ( need to fix TX-ant)\n"));\r
+ }\r
+ }\r
+ else\r
+ #endif\r
+ #endif \r
+ ODM_UpdateRxIdleAnt(pDM_Odm, RxIdleAnt);\r
+ #else\r
+ \r
+ ODM_UpdateRxIdleAnt(pDM_Odm, RxIdleAnt);\r
+ \r
+ #endif//#if(DM_ODM_SUPPORT_TYPE == ODM_AP)\r
+\r
+\r
+\r
+ //2 BDC Main Algorithm\r
+ #ifdef BEAMFORMING_SUPPORT\r
+ #if(DM_ODM_SUPPORT_TYPE == ODM_AP)\r
+ if(pDM_Odm->antdiv_evm_en ==0 ||pDM_FatTable->EVM_method_enable==0)\r
+ {\r
+ odm_BDCcoex_BFeeRxDiv_Arbitration(pDM_Odm);\r
+ }\r
+ #endif\r
+ #endif\r
+\r
if(AntDivMaxRSSI == 0)\r
pDM_DigTable->AntDiv_RSSI_max = pDM_Odm->RSSI_Min;\r
else\r
- pDM_DigTable->AntDiv_RSSI_max = AntDivMaxRSSI;\r
+ pDM_DigTable->AntDiv_RSSI_max = AntDivMaxRSSI;\r
+ \r
pDM_DigTable->RSSI_max = MaxRSSI;\r
}\r
\r
#if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1)\r
VOID\r
odm_S0S1_SwAntDiv(\r
- IN PDM_ODM_T pDM_Odm,\r
+ IN PVOID pDM_VOID, \r
IN u1Byte Step\r
)\r
{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
u4Byte i,MinMaxRSSI=0xFF, LocalMaxRSSI,LocalMinRSSI;\r
u4Byte Main_RSSI, Aux_RSSI;\r
u1Byte reset_period=10, SWAntDiv_threshold=35;\r
u1Byte HighTraffic_TrainTime_U=0x32,HighTraffic_TrainTime_L=0,Train_time_temp;\r
u1Byte LowTraffic_TrainTime_U=200,LowTraffic_TrainTime_L=0;\r
- pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;\r
+ pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;\r
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; \r
u1Byte RxIdleAnt = pDM_SWAT_Table->PreAntenna, TargetAnt, nextAnt=0;\r
PSTA_INFO_T pEntry=NULL;\r
\r
pDM_SWAT_Table->lastTxOkCnt = 0; \r
pDM_SWAT_Table->lastRxOkCnt =0; \r
- TxCntOffset = *(pDM_Odm->pNumTxBytesUnicast);\r
- RxCntOffset = *(pDM_Odm->pNumRxBytesUnicast);\r
+ TxCntOffset = *(pDM_Odm->pNumTxBytesUnicast);\r
+ RxCntOffset = *(pDM_Odm->pNumRxBytesUnicast);\r
\r
pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked;\r
}\r
{\r
\r
//---trafic decision---\r
- curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast) - pDM_SWAT_Table->lastTxOkCnt - TxCntOffset;\r
- curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast) - pDM_SWAT_Table->lastRxOkCnt - RxCntOffset;\r
+ curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast) - pDM_SWAT_Table->lastTxOkCnt - TxCntOffset;\r
+ curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast) - pDM_SWAT_Table->lastRxOkCnt - RxCntOffset;\r
pDM_SWAT_Table->lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast);\r
pDM_SWAT_Table->lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast);\r
\r
if (curTxOkCnt > 1875000 || curRxOkCnt > 1875000)//if(PlatformDivision64(curTxOkCnt+curRxOkCnt, 2) > 1875000) ( 1.875M * 8bit ) / 2= 7.5M bits /sec )\r
{\r
pDM_SWAT_Table->TrafficLoad = TRAFFIC_HIGH;\r
- Train_time_temp=pDM_SWAT_Table->Train_time ;\r
+ Train_time_temp = pDM_SWAT_Table->Train_time ;\r
\r
if(pDM_SWAT_Table->Train_time_flag==3)\r
{\r
{\r
pDM_SWAT_Table->TrafficLoad = TRAFFIC_LOW;\r
Train_time_temp=pDM_SWAT_Table->Train_time ;\r
-\r
+ \r
if(pDM_SWAT_Table->Train_time_flag==3)\r
{\r
LowTraffic_TrainTime_L=10;\r
}\r
else\r
Train_time_temp+=10; \r
-\r
+ \r
//--\r
if(Train_time_temp >= LowTraffic_TrainTime_U)\r
Train_time_temp=LowTraffic_TrainTime_U;\r
Train_time_temp=LowTraffic_TrainTime_L;\r
\r
pDM_SWAT_Table->Train_time = Train_time_temp; //50ms~20ms\r
-\r
+ \r
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,(" Train_time_flag=((%d)) , Train_time=((%d)) \n",pDM_SWAT_Table->Train_time_flag, pDM_SWAT_Table->Train_time));\r
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" [Low Traffic] \n" ));\r
}\r
\r
pDM_SWAT_Table->Double_chk_flag =1;\r
pDM_SWAT_Table->try_flag = 1; \r
- pDM_SWAT_Table->RSSI_Trying = 0;\r
+ pDM_SWAT_Table->RSSI_Trying = 0;\r
\r
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, (" Test the current Ant for (( %d )) ms again \n", pDM_SWAT_Table->Train_time));\r
- ODM_UpdateRxIdleAnt(pDM_Odm, pDM_FatTable->RxIdleAnt); \r
+ ODM_UpdateRxIdleAnt(pDM_Odm, pDM_FatTable->RxIdleAnt);\r
ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer_8723B, pDM_SWAT_Table->Train_time ); //ms \r
return;\r
}\r
pDM_SWAT_Table->RSSI_Trying = 2;\r
else\r
pDM_SWAT_Table->RSSI_Trying = 1;\r
- \r
+\r
odm_S0S1_SwAntDivByCtrlFrame(pDM_Odm, SWAW_STEP_PEAK);\r
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("[set try_flag=1] Normal State: Begin Trying!! \n"));\r
+ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("[set try_flag=1] Normal State: Begin Trying!! \n")); \r
}\r
\r
else if(pDM_SWAT_Table->try_flag == 1 && pDM_SWAT_Table->Double_chk_flag== 0)\r
{\r
BOOLEAN bByCtrlFrame = FALSE;\r
u8Byte pkt_cnt_total = 0;\r
- \r
+ \r
for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)\r
{\r
pEntry = pDM_Odm->pODM_StaInfo[i];\r
\r
if(pDM_FatTable->AuxAnt_Cnt[i]<=1 && pDM_FatTable->CCK_counter_aux>=1)\r
Aux_RSSI=0;\r
-\r
+ \r
TargetAnt = (Main_RSSI==Aux_RSSI)?pDM_SWAT_Table->PreAntenna:((Main_RSSI>=Aux_RSSI)?MAIN_ANT:AUX_ANT);\r
LocalMaxRSSI = (Main_RSSI>=Aux_RSSI) ? Main_RSSI : Aux_RSSI;\r
LocalMinRSSI = (Main_RSSI>=Aux_RSSI) ? Aux_RSSI : Main_RSSI;\r
\r
if (LocalMaxRSSI != 0 && LocalMaxRSSI < MinMaxRSSI)\r
{\r
- RxIdleAnt = TargetAnt;\r
- MinMaxRSSI = LocalMaxRSSI;\r
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** LocalMaxRSSI-LocalMinRSSI = ((%d))\n",(LocalMaxRSSI-LocalMinRSSI)));\r
- \r
- if((LocalMaxRSSI-LocalMinRSSI)>8)\r
+ RxIdleAnt = TargetAnt;\r
+ MinMaxRSSI = LocalMaxRSSI;\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("*** LocalMaxRSSI-LocalMinRSSI = ((%d))\n",(LocalMaxRSSI-LocalMinRSSI)));\r
+ \r
+ if((LocalMaxRSSI-LocalMinRSSI)>8)\r
+ {\r
+ if(LocalMinRSSI != 0)\r
+ pDM_SWAT_Table->Train_time_flag=3;\r
+ else\r
{\r
- if(LocalMinRSSI != 0)\r
- pDM_SWAT_Table->Train_time_flag=3;\r
+ if(MinMaxRSSI > SWAntDiv_threshold)\r
+ pDM_SWAT_Table->Train_time_flag=0;\r
else\r
- {\r
- if(MinMaxRSSI > SWAntDiv_threshold)\r
- pDM_SWAT_Table->Train_time_flag=0;\r
- else\r
- pDM_SWAT_Table->Train_time_flag=3;\r
- }\r
+ pDM_SWAT_Table->Train_time_flag=3;\r
}\r
- else if((LocalMaxRSSI-LocalMinRSSI)>5)\r
- pDM_SWAT_Table->Train_time_flag=2;\r
- else if((LocalMaxRSSI-LocalMinRSSI)>2)\r
- pDM_SWAT_Table->Train_time_flag=1;\r
- else\r
- pDM_SWAT_Table->Train_time_flag=0;\r
+ }\r
+ else if((LocalMaxRSSI-LocalMinRSSI)>5)\r
+ pDM_SWAT_Table->Train_time_flag=2;\r
+ else if((LocalMaxRSSI-LocalMinRSSI)>2)\r
+ pDM_SWAT_Table->Train_time_flag=1;\r
+ else\r
+ pDM_SWAT_Table->Train_time_flag=0;\r
\r
}\r
\r
pDM_FatTable->antsel_a[i] = ANT2_2G;\r
\r
}\r
- pDM_FatTable->MainAnt_Sum[i] = 0;\r
- pDM_FatTable->AuxAnt_Sum[i] = 0;\r
- pDM_FatTable->MainAnt_Cnt[i] = 0;\r
- pDM_FatTable->AuxAnt_Cnt[i] = 0;\r
+ pDM_FatTable->MainAnt_Sum[i] = 0;\r
+ pDM_FatTable->AuxAnt_Sum[i] = 0;\r
+ pDM_FatTable->MainAnt_Cnt[i] = 0;\r
+ pDM_FatTable->AuxAnt_Cnt[i] = 0;\r
}\r
\r
if(pDM_SWAT_Table->bSWAntDivByCtrlFrame)\r
pDM_FatTable->OFDM_counter_aux=0;\r
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Control frame packet counter = %d, Data frame packet counter = %llu\n", \r
pDM_SWAT_Table->PktCnt_SWAntDivByCtrlFrame, pkt_cnt_total));\r
-\r
+ \r
if(MinMaxRSSI == 0xff || ((pkt_cnt_total < (pDM_SWAT_Table->PktCnt_SWAntDivByCtrlFrame >> 1)) && pDM_Odm->PhyDbgInfo.NumQryBeaconPkt < 2))\r
{ \r
MinMaxRSSI = 0;\r
RxIdleAnt = (Main_RSSI==Aux_RSSI)?pDM_SWAT_Table->PreAntenna:((Main_RSSI>=Aux_RSSI)?MAIN_ANT:AUX_ANT);\r
LocalMaxRSSI = (Main_RSSI>=Aux_RSSI) ? Main_RSSI : Aux_RSSI;\r
LocalMinRSSI = (Main_RSSI>=Aux_RSSI) ? Aux_RSSI : Main_RSSI;\r
- \r
+\r
if((LocalMaxRSSI-LocalMinRSSI)>8)\r
pDM_SWAT_Table->Train_time_flag=3;\r
else if((LocalMaxRSSI-LocalMinRSSI)>5)\r
}\r
}\r
}\r
- \r
- pDM_FatTable->MinMaxRSSI=MinMaxRSSI;\r
+\r
+ pDM_FatTable->MinMaxRSSI = MinMaxRSSI;\r
pDM_SWAT_Table->try_flag = 0;\r
\r
if( pDM_SWAT_Table->Double_chk_flag==1)\r
pDM_SWAT_Table->PreAntenna =RxIdleAnt;\r
ODM_UpdateRxIdleAnt(pDM_Odm, RxIdleAnt );\r
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("[reset try_flag = 0] Training accomplished !!!] \n\n\n"));\r
- return;\r
+ return;\r
}\r
\r
}\r
\r
#elif (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
\r
-VOID\r
-ODM_SW_AntDiv_WorkitemCallback(\r
- IN PVOID pContext\r
- )\r
-{\r
- PADAPTER pAdapter = (PADAPTER)pContext;\r
- HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
-\r
- //DbgPrint("SW_antdiv_Workitem_Callback");\r
- odm_S0S1_SwAntDiv(&pHalData->odmpriv, SWAW_STEP_DETERMINE);\r
-}\r
-\r
VOID\r
ODM_SW_AntDiv_Callback(void *FunctionContext)\r
{\r
PDM_ODM_T pDM_Odm= (PDM_ODM_T)FunctionContext;\r
PADAPTER padapter = pDM_Odm->Adapter;\r
-\r
-\r
if(padapter->net_closed == _TRUE)\r
return;\r
-\r
-#if 0 // Can't do I/O in timer callback\r
odm_S0S1_SwAntDiv(pDM_Odm, SWAW_STEP_DETERMINE);\r
-#else\r
- rtw_run_in_thread_cmd(padapter, ODM_SW_AntDiv_WorkitemCallback, padapter);\r
-#endif\r
}\r
\r
-#endif\r
\r
+#endif\r
\r
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))\r
VOID\r
odm_S0S1_SwAntDivByCtrlFrame(\r
- IN PDM_ODM_T pDM_Odm,\r
+ IN PVOID pDM_VOID, \r
IN u1Byte Step\r
)\r
{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;\r
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;\r
\r
\r
VOID\r
odm_AntselStatisticsOfCtrlFrame(\r
- IN PDM_ODM_T pDM_Odm,\r
+ IN PVOID pDM_VOID,\r
IN u1Byte antsel_tr_mux,\r
IN u4Byte RxPWDBAll\r
-)\r
+ \r
+ )\r
{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;\r
\r
if(antsel_tr_mux == ANT1_2G)\r
\r
VOID\r
odm_S0S1_SwAntDivByCtrlFrame_ProcessRSSI(\r
- IN PDM_ODM_T pDM_Odm,\r
- IN PODM_PHY_INFO_T pPhyInfo,\r
- IN PODM_PACKET_INFO_T pPktinfo\r
+ IN PVOID pDM_VOID, \r
+ IN PVOID p_phy_info_void,\r
+ IN PVOID p_pkt_info_void\r
+ //IN PODM_PHY_INFO_T pPhyInfo,\r
+ //IN PODM_PACKET_INFO_T pPktinfo\r
)\r
{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ PODM_PHY_INFO_T pPhyInfo=(PODM_PHY_INFO_T)p_phy_info_void;\r
+ PODM_PACKET_INFO_T pPktinfo=(PODM_PACKET_INFO_T)p_pkt_info_void;\r
pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;\r
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;\r
BOOLEAN isCCKrate;\r
#endif //#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
\r
\r
+#endif //#if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1)\r
\r
-#endif //#if (RTL8723B_SUPPORT == 1)\r
\r
+#if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) )\r
\r
-#if(RTL8188E_SUPPORT == 1 || RTL8192E_SUPPORT == 1)\r
-#if (!(DM_ODM_SUPPORT_TYPE == ODM_CE))\r
VOID\r
odm_SetNextMACAddrTarget(\r
- IN PDM_ODM_T pDM_Odm\r
-)\r
+ IN PVOID pDM_VOID\r
+ )\r
{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;\r
PSTA_INFO_T pEntry;\r
//u1Byte Bssid[6];\r
#else\r
value32 = (pEntry->MacAddr[5]<<8)|pEntry->MacAddr[4];\r
#endif\r
- ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, value32);\r
+ \r
+ ODM_SetMACReg(pDM_Odm, 0x7b4, 0xFFFF, value32);//0x7b4~0x7b5\r
+ \r
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
value32 = (pEntry->hwaddr[3]<<24)|(pEntry->hwaddr[2]<<16) |(pEntry->hwaddr[1]<<8) |pEntry->hwaddr[0];\r
#else\r
value32 = (pEntry->MacAddr[3]<<24)|(pEntry->MacAddr[2]<<16) |(pEntry->MacAddr[1]<<8) |pEntry->MacAddr[0];\r
#endif\r
- ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, value32);\r
+ ODM_SetMACReg(pDM_Odm, 0x7b0, bMaskDWord, value32);//0x7b0~0x7b3\r
\r
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_FatTable->TrainIdx=%lu\n",pDM_FatTable->TrainIdx));\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_FatTable->TrainIdx=%d\n",pDM_FatTable->TrainIdx));\r
+ \r
#if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Training MAC Addr = %x:%x:%x:%x:%x:%x\n",\r
pEntry->hwaddr[5],pEntry->hwaddr[4],pEntry->hwaddr[3],pEntry->hwaddr[2],pEntry->hwaddr[1],pEntry->hwaddr[0]));\r
\r
VOID\r
odm_FastAntTraining(\r
- IN PDM_ODM_T pDM_Odm\r
-)\r
+ IN PVOID pDM_VOID\r
+ )\r
{\r
- u4Byte i, MaxRSSI=0;\r
- u1Byte TargetAnt=2;\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;\r
- BOOLEAN bPktFilterMacth = FALSE;\r
+\r
+ u4Byte MaxRSSI_pathA=0, Pckcnt_pathA=0;\r
+ u1Byte i,TargetAnt_pathA=0;\r
+ BOOLEAN bPktFilterMacth_pathA = FALSE;\r
+ #if(RTL8192E_SUPPORT == 1)\r
+ u4Byte MaxRSSI_pathB=0, Pckcnt_pathB=0;\r
+ u1Byte TargetAnt_pathB=0;\r
+ BOOLEAN bPktFilterMacth_pathB = FALSE;\r
+ #endif\r
+\r
+\r
+ if(!pDM_Odm->bLinked) //bLinked==False\r
+ {\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[No Link!!!]\n"));\r
+ \r
+ if(pDM_FatTable->bBecomeLinked == TRUE)\r
+ {\r
+ odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);\r
+ odm_FastTraining_enable(pDM_Odm , FAT_OFF);\r
+ odm_Tx_By_TxDesc_or_Reg(pDM_Odm , REG);\r
+ pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked;\r
+ }\r
+ return;\r
+ }\r
+ else\r
+ {\r
+ if(pDM_FatTable->bBecomeLinked ==FALSE)\r
+ {\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Linked!!!]\n"));\r
+ odm_Tx_By_TxDesc_or_Reg(pDM_Odm , TX_BY_DESC);\r
+ pDM_FatTable->bBecomeLinked = pDM_Odm->bLinked;\r
+ }\r
+ }\r
+\r
+ \r
+ if(pDM_Odm->SupportICType == ODM_RTL8188E)\r
+ {\r
+ ODM_SetBBReg(pDM_Odm, 0x864 , BIT2|BIT1|BIT0, ((pDM_Odm->fat_comb_a)-1));\r
+ }\r
+ #if(RTL8192E_SUPPORT == 1)\r
+ else if(pDM_Odm->SupportICType == ODM_RTL8192E)\r
+ {\r
+ ODM_SetBBReg(pDM_Odm, 0xB38 , BIT2|BIT1|BIT0, ((pDM_Odm->fat_comb_a)-1) ); //path-A // ant combination=regB38[2:0]+1\r
+ ODM_SetBBReg(pDM_Odm, 0xB38 , BIT18|BIT17|BIT16, ((pDM_Odm->fat_comb_b)-1) ); //path-B // ant combination=regB38[18:16]+1\r
+ }\r
+ #endif\r
\r
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("==>odm_FastAntTraining()\n"));\r
\r
//1 TRAINING STATE\r
if(pDM_FatTable->FAT_State == FAT_TRAINING_STATE)\r
{\r
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Enter FAT_TRAINING_STATE\n"));\r
//2 Caculate RSSI per Antenna\r
- for (i=0; i<7; i++)\r
+\r
+ //3 [path-A]---------------------------\r
+ for (i=0; i<(pDM_Odm->fat_comb_a); i++) // i : antenna index\r
{\r
if(pDM_FatTable->antRSSIcnt[i] == 0)\r
pDM_FatTable->antAveRSSI[i] = 0;\r
else\r
{\r
pDM_FatTable->antAveRSSI[i] = pDM_FatTable->antSumRSSI[i] /pDM_FatTable->antRSSIcnt[i];\r
- bPktFilterMacth = TRUE;\r
+ bPktFilterMacth_pathA = TRUE;\r
}\r
- if(pDM_FatTable->antAveRSSI[i] > MaxRSSI)\r
+ \r
+ if(pDM_FatTable->antAveRSSI[i] > MaxRSSI_pathA)\r
+ {\r
+ MaxRSSI_pathA = pDM_FatTable->antAveRSSI[i];\r
+ Pckcnt_pathA = pDM_FatTable ->antRSSIcnt[i];\r
+ TargetAnt_pathA = i ; \r
+ }\r
+ else if(pDM_FatTable->antAveRSSI[i] == MaxRSSI_pathA)\r
+ {\r
+ if( (pDM_FatTable->antRSSIcnt[i] ) > Pckcnt_pathA)\r
{\r
- MaxRSSI = pDM_FatTable->antAveRSSI[i];\r
- TargetAnt = (u1Byte) i;\r
+ MaxRSSI_pathA = pDM_FatTable->antAveRSSI[i];\r
+ Pckcnt_pathA = pDM_FatTable ->antRSSIcnt[i];\r
+ TargetAnt_pathA = i ;\r
+ }\r
}\r
\r
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_FatTable->antAveRSSI[%lu] = %lu, pDM_FatTable->antRSSIcnt[%lu] = %lu\n",\r
- i, pDM_FatTable->antAveRSSI[i], i, pDM_FatTable->antRSSIcnt[i]));\r
+ ODM_RT_TRACE("*** Ant-Index : [ %d ], Counter = (( %d )), Avg RSSI = (( %d )) \n", i, pDM_FatTable->antRSSIcnt[i], pDM_FatTable->antAveRSSI[i] );\r
}\r
\r
- //2 Select TRX Antenna\r
- if(bPktFilterMacth == FALSE)\r
+\r
+ /*\r
+ #if(RTL8192E_SUPPORT == 1)\r
+ //3 [path-B]---------------------------\r
+ for (i=0; i<(pDM_Odm->fat_comb_b); i++)\r
+ {\r
+ if(pDM_FatTable->antRSSIcnt_pathB[i] == 0)\r
+ pDM_FatTable->antAveRSSI_pathB[i] = 0; \r
+ else // (antRSSIcnt[i] != 0)\r
+ {\r
+ pDM_FatTable->antAveRSSI_pathB[i] = pDM_FatTable->antSumRSSI_pathB[i] /pDM_FatTable->antRSSIcnt_pathB[i];\r
+ bPktFilterMacth_pathB = TRUE;\r
+ }\r
+ if(pDM_FatTable->antAveRSSI_pathB[i] > MaxRSSI_pathB)\r
+ {\r
+ MaxRSSI_pathB = pDM_FatTable->antAveRSSI_pathB[i];\r
+ Pckcnt_pathB = pDM_FatTable ->antRSSIcnt_pathB[i];\r
+ TargetAnt_pathB = (u1Byte) i; \r
+ }\r
+ if(pDM_FatTable->antAveRSSI_pathB[i] == MaxRSSI_pathB)\r
+ {\r
+ if(pDM_FatTable ->antRSSIcnt_pathB > Pckcnt_pathB)\r
{\r
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("None Packet is matched\n"));\r
+ MaxRSSI_pathB = pDM_FatTable->antAveRSSI_pathB[i];\r
+ TargetAnt_pathB = (u1Byte) i;\r
+ } \r
+ }\r
+ if (pDM_Odm->fat_print_rssi==1)\r
+ {\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***{Path-B}: Sum RSSI[%d] = (( %d )), cnt RSSI [%d] = (( %d )), Avg RSSI[%d] = (( %d )) \n",\r
+ i, pDM_FatTable->antSumRSSI_pathB[i], i, pDM_FatTable->antRSSIcnt_pathB[i], i, pDM_FatTable->antAveRSSI_pathB[i]));\r
+ }\r
+ }\r
+ #endif\r
+ */\r
+\r
+ //1 DECISION STATE\r
+\r
+ //2 Select TRX Antenna\r
\r
- ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 0); //RegE08[16]=1'b0 //disable fast training\r
- ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0); //RegC50[7]=1'b0 //disable HW AntDiv\r
+ odm_FastTraining_enable(pDM_Odm , FAT_OFF);\r
+\r
+ //3 [path-A]---------------------------\r
+ if(bPktFilterMacth_pathA == FALSE)\r
+ {\r
+ //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("{Path-A}: None Packet is matched\n"));\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("{Path-A}: None Packet is matched\n"));\r
+ odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);\r
}\r
else\r
{\r
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("TargetAnt=%d, MaxRSSI=%lu\n",TargetAnt,MaxRSSI));\r
-\r
- ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 0); //RegE08[16]=1'b0 //disable fast training\r
- //ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0); //RegC50[7]=1'b0 //disable HW AntDiv\r
- ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, TargetAnt); //Default RX is Omni, Optional RX is the best decision by FAT\r
- //ODM_SetBBReg(pDM_Odm, 0x860 , BIT14|BIT13|BIT12, TargetAnt); //Default TX\r
- ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1); //Reg80c[21]=1'b1 //from TX Info\r
+ ODM_RT_TRACE("TargetAnt_pathA = (( %d )) , MaxRSSI_pathA = (( %d )) \n",TargetAnt_pathA,MaxRSSI_pathA);\r
\r
-#if 0\r
- pEntry = pDM_Odm->pODM_StaInfo[pDM_FatTable->TrainIdx];\r
+ //3 [ update RX-optional ant ] Default RX is Omni, Optional RX is the best decision by FAT\r
+ if(pDM_Odm->SupportICType == ODM_RTL8188E)\r
+ {\r
+ ODM_SetBBReg(pDM_Odm, 0x864 , BIT8|BIT7|BIT6, TargetAnt_pathA); \r
+ }\r
+ else if(pDM_Odm->SupportICType == ODM_RTL8192E)\r
+ {\r
+ ODM_SetBBReg(pDM_Odm, 0xB38 , BIT8|BIT7|BIT6, TargetAnt_pathA);//Optional RX [pth-A]\r
+ }\r
+ //3 [ update TX ant ]\r
+ odm_UpdateTxAnt(pDM_Odm, TargetAnt_pathA, (pDM_FatTable->TrainIdx)); \r
\r
- if(IS_STA_VALID(pEntry))\r
+ if(TargetAnt_pathA == 0)\r
+ odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);\r
+ }\r
+ /*\r
+ #if(RTL8192E_SUPPORT == 1)\r
+ //3 [path-B]---------------------------\r
+ if(bPktFilterMacth_pathB == FALSE)\r
+ {\r
+ if (pDM_Odm->fat_print_rssi==1)\r
+ {\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("***[%d]{Path-B}: None Packet is matched\n\n\n",__LINE__));\r
+ }\r
+ }\r
+ else\r
+ {\r
+ if (pDM_Odm->fat_print_rssi==1)\r
{\r
- pEntry->antsel_a = TargetAnt&BIT0;\r
- pEntry->antsel_b = (TargetAnt&BIT1)>>1;\r
- pEntry->antsel_c = (TargetAnt&BIT2)>>2;\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, \r
+ (" ***TargetAnt_pathB = (( %d )) *** MaxRSSI = (( %d ))***\n\n\n",TargetAnt_pathB,MaxRSSI_pathB));\r
}\r
-#else\r
- pDM_FatTable->antsel_a[pDM_FatTable->TrainIdx] = TargetAnt&BIT0;\r
- pDM_FatTable->antsel_b[pDM_FatTable->TrainIdx] = (TargetAnt&BIT1)>>1;\r
- pDM_FatTable->antsel_c[pDM_FatTable->TrainIdx] = (TargetAnt&BIT2)>>2;\r
-#endif\r
-\r
-\r
- if(TargetAnt == 0)\r
- ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 0); //RegC50[7]=1'b0 //disable HW AntDiv\r
+ ODM_SetBBReg(pDM_Odm, 0xB38 , BIT21|BIT20|BIT19, TargetAnt_pathB); //Default RX is Omni, Optional RX is the best decision by FAT \r
+ ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1); //Reg80c[21]=1'b1 //from TX Info\r
\r
+ pDM_FatTable->antsel_pathB[pDM_FatTable->TrainIdx] = TargetAnt_pathB;\r
}\r
+ #endif\r
+ */\r
\r
//2 Reset Counter\r
- for(i=0; i<7; i++)\r
+ for(i=0; i<(pDM_Odm->fat_comb_a); i++)\r
{\r
pDM_FatTable->antSumRSSI[i] = 0;\r
pDM_FatTable->antRSSIcnt[i] = 0;\r
}\r
+ /*\r
+ #if(RTL8192E_SUPPORT == 1)\r
+ for(i=0; i<=(pDM_Odm->fat_comb_b); i++)\r
+ {\r
+ pDM_FatTable->antSumRSSI_pathB[i] = 0;\r
+ pDM_FatTable->antRSSIcnt_pathB[i] = 0;\r
+ }\r
+ #endif\r
+ */\r
\r
pDM_FatTable->FAT_State = FAT_NORMAL_STATE;\r
return;\r
//1 NORMAL STATE\r
if(pDM_FatTable->FAT_State == FAT_NORMAL_STATE)\r
{\r
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Enter FAT_NORMAL_STATE\n"));\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Start Normal State]\n"));\r
\r
odm_SetNextMACAddrTarget(pDM_Odm);\r
\r
-#if 0\r
- pEntry = pDM_Odm->pODM_StaInfo[pDM_FatTable->TrainIdx];\r
- if(IS_STA_VALID(pEntry))\r
- {\r
- pEntry->antsel_a = TargetAnt&BIT0;\r
- pEntry->antsel_b = (TargetAnt&BIT1)>>1;\r
- pEntry->antsel_c = (TargetAnt&BIT2)>>2;\r
- }\r
-#endif\r
-\r
//2 Prepare Training\r
pDM_FatTable->FAT_State = FAT_TRAINING_STATE;\r
- ODM_SetBBReg(pDM_Odm, 0xe08 , BIT16, 1); //RegE08[16]=1'b1 //enable fast training\r
- ODM_SetBBReg(pDM_Odm, 0xc50 , BIT7, 1); //RegC50[7]=1'b1 //enable HW AntDiv\r
- ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Start FAT_TRAINING_STATE\n"));\r
- ODM_SetTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer, 500 ); //ms\r
- \r
+ odm_FastTraining_enable(pDM_Odm , FAT_ON);\r
+ odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON); //enable HW AntDiv\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[Start Training State]\n"));\r
+\r
+ ODM_SetTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer, pDM_Odm->antdiv_intvl ); //ms\r
}\r
\r
}\r
\r
VOID\r
odm_FastAntTrainingCallback(\r
- IN PDM_ODM_T pDM_Odm\r
-)\r
+ IN PVOID pDM_VOID\r
+ )\r
{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
\r
#if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
PADAPTER padapter = pDM_Odm->Adapter;\r
#if USE_WORKITEM\r
ODM_ScheduleWorkItem(&pDM_Odm->FastAntTrainingWorkitem);\r
#else\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("******odm_FastAntTrainingCallback****** \n"));\r
odm_FastAntTraining(pDM_Odm);\r
#endif\r
}\r
\r
VOID\r
odm_FastAntTrainingWorkItemCallback(\r
- IN PDM_ODM_T pDM_Odm\r
-)\r
+ IN PVOID pDM_VOID\r
+ )\r
{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("******odm_FastAntTrainingWorkItemCallback****** \n"));\r
odm_FastAntTraining(pDM_Odm);\r
}\r
-#endif\r
-\r
-#endif\r
\r
-VOID\r
-ODM_AntDivReset(\r
- IN PDM_ODM_T pDM_Odm \r
- )\r
-{\r
- //2 [--8723B---]\r
-#if (RTL8723B_SUPPORT == 1)\r
- if(pDM_Odm->SupportICType == ODM_RTL8723B)\r
- odm_S0S1_SWAntDiv_Reset_8723B(pDM_Odm);\r
#endif\r
-}\r
\r
VOID\r
ODM_AntDivInit(\r
- IN PDM_ODM_T pDM_Odm \r
+ IN PVOID pDM_VOID\r
)\r
{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;\r
pSWAT_T pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;\r
\r
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[2G & 5G AntDiv Init]:Support Both 2G & 5G Antenna Diversity Function\n"));\r
}\r
\r
- pDM_Odm->antdiv_rssi=0;\r
-\r
#endif \r
//---\r
- \r
+\r
//2 [--General---]\r
pDM_Odm->antdiv_period=0;\r
- pDM_Odm->antdiv_select=0;\r
- pDM_SWAT_Table->Ant5G = MAIN_ANT;\r
- pDM_SWAT_Table->Ant2G = MAIN_ANT;\r
- pDM_FatTable->CCK_counter_main=0;\r
- pDM_FatTable->CCK_counter_aux=0;\r
- pDM_FatTable->OFDM_counter_main=0;\r
- pDM_FatTable->OFDM_counter_aux=0;\r
- \r
- //3 [Set MAIN_ANT as default antenna if Auto-Ant enable]\r
- if (pDM_Odm->antdiv_select==1)\r
- pDM_Odm->AntType = ODM_FIX_MAIN_ANT;\r
- else if (pDM_Odm->antdiv_select==2)\r
- pDM_Odm->AntType = ODM_FIX_AUX_ANT;\r
- else if(pDM_Odm->antdiv_select==0)\r
- pDM_Odm->AntType = ODM_AUTO_ANT;\r
+\r
+ pDM_FatTable->bBecomeLinked =FALSE;\r
+ pDM_FatTable->AntDiv_OnOff =0xff;\r
+\r
+ //3 - AP -\r
+ #if (DM_ODM_SUPPORT_TYPE == ODM_AP)\r
\r
- if(pDM_Odm->AntType == ODM_AUTO_ANT)\r
- {\r
- odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);\r
- ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);\r
- }\r
- else\r
- {\r
- odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);\r
+ #ifdef BEAMFORMING_SUPPORT\r
+ #if(DM_ODM_SUPPORT_TYPE == ODM_AP)\r
+ odm_BDC_Init(pDM_Odm);\r
+ #endif\r
+ #endif\r
\r
- if(pDM_Odm->AntType == ODM_FIX_MAIN_ANT)\r
- {\r
- ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);\r
- return;\r
- }\r
- else if(pDM_Odm->AntType == ODM_FIX_AUX_ANT)\r
- {\r
- ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT);\r
- return;\r
- }\r
- }\r
- //---\r
- if(pDM_Odm->AntDivType != CGCS_RX_HW_ANTDIV)\r
- {\r
- if(pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT)\r
- {\r
- #if TX_BY_REG\r
- ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 0); //Reg80c[21]=1'b0 //from Reg\r
- #else\r
- ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1);\r
- #endif\r
- } \r
- else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT)\r
- {\r
- #if TX_BY_REG\r
- ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 0); \r
- #else\r
- ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 1); \r
- #endif\r
- }\r
- }\r
+ //3 - WIN -\r
+ #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
+ pDM_SWAT_Table->Ant5G = MAIN_ANT;\r
+ pDM_SWAT_Table->Ant2G = MAIN_ANT;\r
+ pDM_FatTable->CCK_counter_main=0;\r
+ pDM_FatTable->CCK_counter_aux=0;\r
+ pDM_FatTable->OFDM_counter_main=0;\r
+ pDM_FatTable->OFDM_counter_aux=0;\r
+ #endif\r
+\r
+ //2 [---Set MAIN_ANT as default antenna if Auto-Ant enable---]\r
+ odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);\r
+\r
+ pDM_Odm->AntType = ODM_AUTO_ANT;\r
+\r
+ pDM_FatTable->RxIdleAnt = ANTDIV_INIT;\r
+ ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);\r
+ \r
+ //2 [---Set TX Antenna---]\r
+ odm_Tx_By_TxDesc_or_Reg(pDM_Odm , REG);\r
+\r
\r
//2 [--88E---]\r
if(pDM_Odm->SupportICType == ODM_RTL8188E)\r
odm_RX_HWAntDiv_Init_88E(pDM_Odm);\r
else if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)\r
odm_TRX_HWAntDiv_Init_88E(pDM_Odm);\r
+ #if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) )\r
else if(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)\r
odm_Smart_HWAntDiv_Init_88E(pDM_Odm);\r
- #endif \r
+ #endif \r
+ #endif\r
}\r
\r
//2 [--92E---]\r
odm_RX_HWAntDiv_Init_92E(pDM_Odm);\r
else if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)\r
odm_TRX_HWAntDiv_Init_92E(pDM_Odm);\r
+ #if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) )\r
else if(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)\r
odm_Smart_HWAntDiv_Init_92E(pDM_Odm);\r
+ #endif\r
\r
}\r
#endif \r
\r
VOID\r
ODM_AntDiv(\r
- IN PDM_ODM_T pDM_Odm\r
-)\r
-{ \r
+ IN PVOID pDM_VOID\r
+ )\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
PADAPTER pAdapter = pDM_Odm->Adapter;\r
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;\r
\r
-//#if (DM_ODM_SUPPORT_TYPE == ODM_AP) \r
if(*pDM_Odm->pBandType == ODM_BAND_5G )\r
{\r
if(pDM_FatTable->idx_AntDiv_counter_5G < pDM_Odm->antdiv_period )\r
else\r
pDM_FatTable->idx_AntDiv_counter_2G=0;\r
}\r
-//#endif \r
+ \r
//----------\r
if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))\r
{\r
if( BeamformCap & BEAMFORMEE_CAP ) // BFmee On && Div On -> Div Off\r
{ \r
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ AntDiv : OFF ] BFmee ==1 \n"));\r
- if(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)\r
+ if(pDM_FatTable->fix_ant_bfee == 0)\r
{\r
odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);\r
- pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV);\r
- return;\r
+ pDM_FatTable->fix_ant_bfee = 1;\r
}\r
+ return;\r
}\r
else // BFmee Off && Div Off -> Div On\r
- #endif\r
{\r
- if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV) && pDM_Odm->bLinked) \r
+ if((pDM_FatTable->fix_ant_bfee == 1) && pDM_Odm->bLinked) \r
{\r
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ AntDiv : ON ] BFmee ==0 \n"));\r
+ ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ AntDiv : ON ] BFmee ==0\n"));\r
if((pDM_Odm->AntDivType!=S0S1_SW_ANTDIV) )\r
odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON);\r
- \r
- pDM_Odm->SupportAbility |= (ODM_BB_ANT_DIV);\r
+\r
+ pDM_FatTable->fix_ant_bfee = 0;\r
}\r
}\r
- }\r
-#endif\r
+ }\r
+ #endif \r
+#elif (DM_ODM_SUPPORT_TYPE == ODM_AP)\r
+ //----------just for fool proof\r
+\r
+ if(pDM_Odm->antdiv_rssi)\r
+ pDM_Odm->DebugComponents |= ODM_COMP_ANT_DIV;\r
+ else\r
+ pDM_Odm->DebugComponents &= ~ODM_COMP_ANT_DIV;\r
\r
- //----------\r
-#if (DM_ODM_SUPPORT_TYPE == ODM_AP)\r
if(pDM_FatTable->AntDiv_2G_5G == ODM_ANTDIV_2G)\r
{\r
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ 2G AntDiv Running ]\n"));\r
+ //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ 2G AntDiv Running ]\n"));\r
if(!(pDM_Odm->SupportICType & ODM_ANTDIV_2G_SUPPORT_IC))\r
return;\r
}\r
else if(pDM_FatTable->AntDiv_2G_5G == ODM_ANTDIV_5G)\r
{\r
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ 5G AntDiv Running ]\n"));\r
+ //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ 5G AntDiv Running ]\n"));\r
if(!(pDM_Odm->SupportICType & ODM_ANTDIV_5G_SUPPORT_IC))\r
- return;\r
- }\r
- else if(pDM_FatTable->AntDiv_2G_5G == (ODM_ANTDIV_2G|ODM_ANTDIV_5G))\r
- {\r
- ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ 2G & 5G AntDiv Running ]\n"));\r
+ return;\r
}\r
+ //else if(pDM_FatTable->AntDiv_2G_5G == (ODM_ANTDIV_2G|ODM_ANTDIV_5G))\r
+ //{\r
+ //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("[ 2G & 5G AntDiv Running ]\n"));\r
+ //}\r
#endif\r
\r
//----------\r
pDM_Odm->AntType = ODM_FIX_MAIN_ANT;\r
else if (pDM_Odm->antdiv_select==2)\r
pDM_Odm->AntType = ODM_FIX_AUX_ANT;\r
- else if (pDM_Odm->antdiv_select==0)\r
+ else //if (pDM_Odm->antdiv_select==0)\r
pDM_Odm->AntType = ODM_AUTO_ANT;\r
\r
//ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("AntType= (( %d )) , pre_AntType= (( %d )) \n",pDM_Odm->AntType,pDM_Odm->pre_AntType));\r
if(pDM_Odm->AntType != pDM_Odm->pre_AntType)\r
{\r
odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);\r
-\r
- if(pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT)\r
- ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 0);\r
- else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT)\r
- ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 0); \r
+ odm_Tx_By_TxDesc_or_Reg(pDM_Odm , REG);\r
\r
if(pDM_Odm->AntType == ODM_FIX_MAIN_ANT)\r
ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);\r
if(pDM_Odm->AntType != pDM_Odm->pre_AntType)\r
{\r
odm_AntDiv_on_off(pDM_Odm, ANTDIV_ON);\r
- if(pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT)\r
- ODM_SetBBReg(pDM_Odm, 0x80c , BIT21, 1);\r
- else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT)\r
- ODM_SetBBReg(pDM_Odm, 0x900 , BIT18, 1); \r
+ odm_Tx_By_TxDesc_or_Reg(pDM_Odm , TX_BY_DESC);\r
}\r
pDM_Odm->pre_AntType=pDM_Odm->AntType;\r
}\r
#if (RTL8188E_SUPPORT == 1)\r
if(pDM_Odm->AntDivType==CG_TRX_HW_ANTDIV ||pDM_Odm->AntDivType==CGCS_RX_HW_ANTDIV)\r
odm_HW_AntDiv(pDM_Odm);\r
- #if (!(DM_ODM_SUPPORT_TYPE == ODM_CE))\r
+\r
+ #if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) )\r
else if (pDM_Odm->AntDivType==CG_TRX_SMART_ANTDIV)\r
odm_FastAntTraining(pDM_Odm); \r
#endif\r
+ \r
#endif\r
+\r
}\r
//2 [--92E---] \r
#if (RTL8192E_SUPPORT == 1)\r
else if(pDM_Odm->SupportICType == ODM_RTL8192E)\r
{\r
- if(pDM_Odm->AntDivType==CGCS_RX_HW_ANTDIV)\r
+ if(pDM_Odm->AntDivType==CGCS_RX_HW_ANTDIV || pDM_Odm->AntDivType==CG_TRX_HW_ANTDIV)\r
odm_HW_AntDiv(pDM_Odm);\r
- #if (!(DM_ODM_SUPPORT_TYPE == ODM_CE))\r
+ \r
+ #if( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) )\r
else if (pDM_Odm->AntDivType==CG_TRX_SMART_ANTDIV)\r
odm_FastAntTraining(pDM_Odm); \r
#endif\r
+ \r
}\r
#endif\r
\r
{\r
if(pDM_Odm->AntDivType == S0S1_SW_ANTDIV)\r
{\r
- pDM_Odm->AntDivType=CG_TRX_HW_ANTDIV;\r
+ pDM_Odm->AntDivType=CG_TRX_HW_ANTDIV;\r
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,(" [S0S1_SW_ANTDIV] -> [CG_TRX_HW_ANTDIV]\n"));\r
//ODM_SetBBReg(pDM_Odm, 0x8D4 , BIT24, 1); \r
if(pDM_FatTable->bBecomeLinked ==TRUE)\r
{\r
if(pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)\r
{\r
- pDM_Odm->AntDivType=S0S1_SW_ANTDIV;\r
+ pDM_Odm->AntDivType=S0S1_SW_ANTDIV;\r
ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,(" [CG_TRX_HW_ANTDIV] -> [S0S1_SW_ANTDIV]\n"));\r
//ODM_SetBBReg(pDM_Odm, 0x8D4 , BIT24, 0);\r
odm_AntDiv_on_off(pDM_Odm, ANTDIV_OFF);\r
if (pDM_Odm->AntDivType==S0S1_SW_ANTDIV)\r
odm_S0S1_SwAntDiv(pDM_Odm, SWAW_STEP_PEAK);\r
else if (pDM_Odm->AntDivType==CG_TRX_HW_ANTDIV)\r
- odm_HW_AntDiv(pDM_Odm);\r
+ odm_HW_AntDiv(pDM_Odm);\r
}\r
#endif\r
+ \r
//2 [--8881A---]\r
#if (RTL8881A_SUPPORT == 1)\r
else if(pDM_Odm->SupportICType == ODM_RTL8881A) \r
odm_HW_AntDiv(pDM_Odm);\r
#endif\r
+ \r
//2 [--8812A---]\r
#if (RTL8812A_SUPPORT == 1)\r
else if(pDM_Odm->SupportICType == ODM_RTL8812)\r
\r
VOID\r
odm_AntselStatistics(\r
- IN PDM_ODM_T pDM_Odm,\r
+ IN PVOID pDM_VOID, \r
IN u1Byte antsel_tr_mux,\r
IN u4Byte MacId,\r
- IN u4Byte RxPWDBAll\r
-)\r
+ IN u4Byte utility,\r
+ IN u1Byte method\r
+\r
+ )\r
{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;\r
-\r
- if(antsel_tr_mux == ANT1_2G)\r
+ if(method==RSSI_METHOD)\r
+ {\r
+ if(antsel_tr_mux == ANT1_2G)\r
+ {\r
+ pDM_FatTable->MainAnt_Sum[MacId]+=utility;\r
+ pDM_FatTable->MainAnt_Cnt[MacId]++;\r
+ }\r
+ else\r
+ {\r
+ pDM_FatTable->AuxAnt_Sum[MacId]+=utility;\r
+ pDM_FatTable->AuxAnt_Cnt[MacId]++;\r
+ }\r
+ }\r
+ #ifdef ODM_EVM_ENHANCE_ANTDIV\r
+ else if(method==EVM_METHOD)\r
{\r
- pDM_FatTable->MainAnt_Sum[MacId]+=RxPWDBAll;\r
- pDM_FatTable->MainAnt_Cnt[MacId]++;\r
+ if(antsel_tr_mux == ANT1_2G)\r
+ {\r
+ pDM_FatTable->MainAntEVM_Sum[MacId]+=(utility<<5);\r
+ pDM_FatTable->MainAntEVM_Cnt[MacId]++;\r
+ }\r
+ else\r
+ {\r
+ pDM_FatTable->AuxAntEVM_Sum[MacId]+=(utility<<5);\r
+ pDM_FatTable->AuxAntEVM_Cnt[MacId]++;\r
+ }\r
}\r
- else\r
+ else if(method==CRC32_METHOD)\r
{\r
- pDM_FatTable->AuxAnt_Sum[MacId]+=RxPWDBAll;\r
- pDM_FatTable->AuxAnt_Cnt[MacId]++;\r
+ if(utility==0)\r
+ pDM_FatTable->CRC32_Fail_Cnt++;\r
+ else\r
+ pDM_FatTable->CRC32_Ok_Cnt+=utility;\r
}\r
+ #endif\r
}\r
\r
\r
VOID\r
ODM_Process_RSSIForAntDiv( \r
- IN OUT PDM_ODM_T pDM_Odm,\r
- IN PODM_PHY_INFO_T pPhyInfo,\r
- IN PODM_PACKET_INFO_T pPktinfo\r
+ IN OUT PVOID pDM_VOID, \r
+ IN PVOID p_phy_info_void,\r
+ IN PVOID p_pkt_info_void\r
+ //IN PODM_PHY_INFO_T pPhyInfo,\r
+ //IN PODM_PACKET_INFO_T pPktinfo\r
)\r
{\r
-u1Byte isCCKrate=0,CCKMaxRate=DESC_RATE11M;\r
-pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ PODM_PHY_INFO_T pPhyInfo=(PODM_PHY_INFO_T)p_phy_info_void;\r
+ PODM_PACKET_INFO_T pPktinfo=(PODM_PACKET_INFO_T)p_pkt_info_void;\r
+ u1Byte isCCKrate=0,CCKMaxRate=ODM_RATE11M;\r
+ pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;\r
\r
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))\r
u4Byte RxPower_Ant0, RxPower_Ant1; \r
+ u4Byte RxEVM_Ant0, RxEVM_Ant1;\r
#else\r
u1Byte RxPower_Ant0, RxPower_Ant1; \r
+ u1Byte RxEVM_Ant0, RxEVM_Ant1;\r
#endif\r
\r
- if(pDM_Odm->SupportICType & ODM_N_ANTDIV_SUPPORT)\r
- CCKMaxRate=DESC_RATE11M;\r
- else if(pDM_Odm->SupportICType & ODM_AC_ANTDIV_SUPPORT)\r
- CCKMaxRate=DESC_RATE11M;\r
+ CCKMaxRate=ODM_RATE11M;\r
isCCKrate = (pPktinfo->DataRate <= CCKMaxRate)?TRUE:FALSE;\r
\r
#if ((RTL8192C_SUPPORT == 1) ||(RTL8192D_SUPPORT == 1))\r
{\r
if(pPktinfo->bPacketToSelf || pPktinfo->bPacketBeacon)\r
{\r
- //if(pPktinfo->bPacketBeacon)\r
- //{\r
- // DbgPrint("This is beacon, isCCKrate=%d\n", isCCKrate);\r
- //}\r
ODM_AntselStatistics_88C(pDM_Odm, pPktinfo->StationID, pPhyInfo->RxPWDBAll, isCCKrate);\r
}\r
}\r
{\r
RxPower_Ant0 = pPhyInfo->RxMIMOSignalStrength[0];\r
RxPower_Ant1= pPhyInfo->RxMIMOSignalStrength[1];\r
+\r
+ RxEVM_Ant0 =pPhyInfo->RxMIMOSignalQuality[0];\r
+ RxEVM_Ant1 =pPhyInfo->RxMIMOSignalQuality[1];\r
}\r
else\r
RxPower_Ant0=pPhyInfo->RxPWDBAll;\r
\r
if(pDM_Odm->AntDivType == CG_TRX_SMART_ANTDIV)\r
{\r
- if( (pDM_Odm->SupportICType & ODM_SMART_ANT_SUPPORT) && pPktinfo->bPacketToSelf && pDM_FatTable->FAT_State == FAT_TRAINING_STATE )//(pPktinfo->bPacketMatchBSSID && (!pPktinfo->bPacketBeacon))\r
+ if( (pDM_Odm->SupportICType & ODM_SMART_ANT_SUPPORT) && (pPktinfo->bPacketToSelf) && (pDM_FatTable->FAT_State == FAT_TRAINING_STATE) )//(pPktinfo->bPacketMatchBSSID && (!pPktinfo->bPacketBeacon))\r
{\r
u1Byte antsel_tr_mux;\r
antsel_tr_mux = (pDM_FatTable->antsel_rx_keep_2<<2) |(pDM_FatTable->antsel_rx_keep_1 <<1) |pDM_FatTable->antsel_rx_keep_0;\r
{\r
if( ( pDM_Odm->SupportICType & ODM_ANTDIV_SUPPORT ) && (pPktinfo->bPacketToSelf || pPktinfo->bPacketMatchBSSID) )\r
{\r
- if(pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8192E)\r
- odm_AntselStatistics(pDM_Odm, pDM_FatTable->antsel_rx_keep_0, pPktinfo->StationID,RxPower_Ant0);\r
+ if(pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8192E)\r
+ {\r
+ odm_AntselStatistics(pDM_Odm, pDM_FatTable->antsel_rx_keep_0, pPktinfo->StationID,RxPower_Ant0,RSSI_METHOD);\r
+\r
+ #ifdef ODM_EVM_ENHANCE_ANTDIV\r
+ if(!isCCKrate)\r
+ {\r
+ odm_AntselStatistics(pDM_Odm, pDM_FatTable->antsel_rx_keep_0, pPktinfo->StationID,RxEVM_Ant0,EVM_METHOD);\r
+ }\r
+ #endif\r
+ }\r
else// SupportICType == ODM_RTL8821 and ODM_RTL8723B and ODM_RTL8812)\r
{\r
if(isCCKrate && (pDM_Odm->AntDivType == S0S1_SW_ANTDIV))\r
pDM_FatTable->antsel_rx_keep_0 = (pDM_FatTable->RxIdleAnt == MAIN_ANT) ? ANT1_2G : ANT2_2G;\r
\r
\r
- if(pDM_FatTable->antsel_rx_keep_0==ANT1_2G)\r
- pDM_FatTable->CCK_counter_main++;\r
- else// if(pDM_FatTable->antsel_rx_keep_0==ANT2_2G)\r
- pDM_FatTable->CCK_counter_aux++;\r
+ if(pDM_FatTable->antsel_rx_keep_0==ANT1_2G)\r
+ pDM_FatTable->CCK_counter_main++;\r
+ else// if(pDM_FatTable->antsel_rx_keep_0==ANT2_2G)\r
+ pDM_FatTable->CCK_counter_aux++;\r
\r
- odm_AntselStatistics(pDM_Odm, pDM_FatTable->antsel_rx_keep_0, pPktinfo->StationID, RxPower_Ant0);\r
+ odm_AntselStatistics(pDM_Odm, pDM_FatTable->antsel_rx_keep_0, pPktinfo->StationID, RxPower_Ant0,RSSI_METHOD);\r
}\r
else\r
{\r
pDM_FatTable->OFDM_counter_main++;\r
else// if(pDM_FatTable->antsel_rx_keep_0==ANT2_2G)\r
pDM_FatTable->OFDM_counter_aux++;\r
- odm_AntselStatistics(pDM_Odm, pDM_FatTable->antsel_rx_keep_0, pPktinfo->StationID, RxPower_Ant0);\r
+ odm_AntselStatistics(pDM_Odm, pDM_FatTable->antsel_rx_keep_0, pPktinfo->StationID, RxPower_Ant0,RSSI_METHOD);\r
+ }\r
}\r
}\r
}\r
- }\r
//ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("isCCKrate=%d, PWDB_ALL=%d\n",isCCKrate, pPhyInfo->RxPWDBAll));\r
//ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("antsel_tr_mux=3'b%d%d%d\n",pDM_FatTable->antsel_rx_keep_2, pDM_FatTable->antsel_rx_keep_1, pDM_FatTable->antsel_rx_keep_0));\r
}\r
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))\r
VOID\r
ODM_SetTxAntByTxInfo(\r
- IN PDM_ODM_T pDM_Odm,\r
+ IN PVOID pDM_VOID, \r
IN pu1Byte pDesc,\r
IN u1Byte macId \r
-)\r
+\r
+ )\r
{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;\r
\r
- if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))\r
+ if (!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))\r
return;\r
\r
- if(pDM_Odm->AntDivType==CGCS_RX_HW_ANTDIV)\r
+ if (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)\r
return;\r
\r
\r
- if(pDM_Odm->SupportICType == ODM_RTL8723B)\r
- {\r
- #if (RTL8723B_SUPPORT == 1)\r
+ if (pDM_Odm->SupportICType == ODM_RTL8723B) {\r
+#if (RTL8723B_SUPPORT == 1)\r
SET_TX_DESC_ANTSEL_A_8723B(pDesc, pDM_FatTable->antsel_a[macId]);\r
- //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8723B] SetTxAntByTxInfo_WIN: MacID=%d, antsel_tr_mux=3'b%d%d%d\n", \r
- //macId, pDM_FatTable->antsel_c[macId], pDM_FatTable->antsel_b[macId], pDM_FatTable->antsel_a[macId]));\r
- #endif\r
- }\r
- else if(pDM_Odm->SupportICType == ODM_RTL8821)\r
- {\r
- #if (RTL8821A_SUPPORT == 1)\r
+ /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8723B] SetTxAntByTxInfo_WIN: MacID=%d, antsel_tr_mux=3'b%d%d%d\n", \r
+ macId, pDM_FatTable->antsel_c[macId], pDM_FatTable->antsel_b[macId], pDM_FatTable->antsel_a[macId]));*/\r
+#endif\r
+ } else if (pDM_Odm->SupportICType == ODM_RTL8821) {\r
+#if (RTL8821A_SUPPORT == 1)\r
SET_TX_DESC_ANTSEL_A_8812(pDesc, pDM_FatTable->antsel_a[macId]);\r
- //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8821A] SetTxAntByTxInfo_WIN: MacID=%d, antsel_tr_mux=3'b%d%d%d\n", \r
- //macId, pDM_FatTable->antsel_c[macId], pDM_FatTable->antsel_b[macId], pDM_FatTable->antsel_a[macId]));\r
- #endif\r
- }\r
- else if(pDM_Odm->SupportICType == ODM_RTL8188E)\r
- {\r
- #if (RTL8188E_SUPPORT == 1)\r
+ /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8821A] SetTxAntByTxInfo_WIN: MacID=%d, antsel_tr_mux=3'b%d%d%d\n", \r
+ macId, pDM_FatTable->antsel_c[macId], pDM_FatTable->antsel_b[macId], pDM_FatTable->antsel_a[macId]));*/\r
+#endif\r
+ } else if (pDM_Odm->SupportICType == ODM_RTL8188E) {\r
+#if (RTL8188E_SUPPORT == 1)\r
SET_TX_DESC_ANTSEL_A_88E(pDesc, pDM_FatTable->antsel_a[macId]);\r
SET_TX_DESC_ANTSEL_B_88E(pDesc, pDM_FatTable->antsel_b[macId]);\r
SET_TX_DESC_ANTSEL_C_88E(pDesc, pDM_FatTable->antsel_c[macId]);\r
- //ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8188E] SetTxAntByTxInfo_WIN: MacID=%d, antsel_tr_mux=3'b%d%d%d\n", \r
- //macId, pDM_FatTable->antsel_c[macId], pDM_FatTable->antsel_b[macId], pDM_FatTable->antsel_a[macId]));\r
- #endif\r
- }\r
- else if(pDM_Odm->SupportICType == ODM_RTL8192E)\r
- {\r
-\r
- \r
+ /*ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[8188E] SetTxAntByTxInfo_WIN: MacID=%d, antsel_tr_mux=3'b%d%d%d\n", \r
+ macId, pDM_FatTable->antsel_c[macId], pDM_FatTable->antsel_b[macId], pDM_FatTable->antsel_a[macId]));*/\r
+#endif\r
}\r
}\r
-#else// (DM_ODM_SUPPORT_TYPE == ODM_AP)\r
+#elif(DM_ODM_SUPPORT_TYPE == ODM_AP)\r
\r
VOID\r
ODM_SetTxAntByTxInfo(\r
- //IN PDM_ODM_T pDM_Odm,\r
struct rtl8192cd_priv *priv,\r
- struct tx_desc *pdesc,\r
- struct tx_insn *txcfg,\r
+ struct tx_desc *pdesc,\r
unsigned short aid \r
)\r
{\r
pFAT_T pDM_FatTable = &priv->pshare->_dmODM.DM_FatTable;\r
- u4Byte SupportICType=priv->pshare->_dmODM.SupportICType;\r
+ u4Byte SupportICType = priv->pshare->_dmODM.SupportICType;\r
\r
- if(SupportICType == ODM_RTL8881A)\r
- {\r
- //panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8881E****** \n",__FUNCTION__,__LINE__); \r
- pdesc->Dword6 &= set_desc(~ (BIT(18)|BIT(17)|BIT(16))); \r
+ if (SupportICType == ODM_RTL8881A) {\r
+ /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8881E******\n",__FUNCTION__,__LINE__); */\r
+ pdesc->Dword6 &= set_desc(~(BIT(18)|BIT(17)|BIT(16))); \r
pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_a[aid]<<16);\r
- }\r
- else if(SupportICType == ODM_RTL8192E)\r
- {\r
- //panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8192E****** \n",__FUNCTION__,__LINE__); \r
- pdesc->Dword6 &= set_desc(~ (BIT(18)|BIT(17)|BIT(16))); \r
+ } else if (SupportICType == ODM_RTL8192E) {\r
+ /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8192E******\n",__FUNCTION__,__LINE__); */\r
+ pdesc->Dword6 &= set_desc(~(BIT(18)|BIT(17)|BIT(16))); \r
pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_a[aid]<<16);\r
- }\r
- else if(SupportICType == ODM_RTL8812)\r
- {\r
- //3 [path-A]\r
- //panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8881E****** \n",__FUNCTION__,__LINE__);\r
+ } else if (SupportICType == ODM_RTL8188E) {\r
+ /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8188E******\n",__FUNCTION__,__LINE__);*/\r
+ pdesc->Dword2 &= set_desc(~BIT(24));\r
+ pdesc->Dword2 &= set_desc(~BIT(25));\r
+ pdesc->Dword7 &= set_desc(~BIT(29));\r
+\r
+ pdesc->Dword2 |= set_desc(pDM_FatTable->antsel_a[aid]<<24);\r
+ pdesc->Dword2 |= set_desc(pDM_FatTable->antsel_b[aid]<<25);\r
+ pdesc->Dword7 |= set_desc(pDM_FatTable->antsel_c[aid]<<29);\r
+ \r
+ \r
+ } else if (SupportICType == ODM_RTL8812) {\r
+ /*[path-A]*/\r
+ /*panic_printk("[%s] [%d] ******ODM_SetTxAntByTxInfo_8881E******\n",__FUNCTION__,__LINE__);*/\r
+ \r
+ pdesc->Dword6 &= set_desc(~BIT(16));\r
+ pdesc->Dword6 &= set_desc(~BIT(17));\r
+ pdesc->Dword6 &= set_desc(~BIT(18));\r
+\r
+ pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_a[aid]<<16);\r
+ pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_b[aid]<<17);\r
+ pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_c[aid]<<18);\r
\r
- pdesc->Dword6 &= set_desc(~ BIT(16));\r
- pdesc->Dword6 &= set_desc(~ BIT(17));\r
- pdesc->Dword6 &= set_desc(~ BIT(18));\r
- if(txcfg->pstat)\r
- {\r
- pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_a[aid]<<16);\r
- pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_b[aid]<<17);\r
- pdesc->Dword6 |= set_desc(pDM_FatTable->antsel_c[aid]<<18);\r
- }\r
}\r
}\r
#endif\r
\r
VOID\r
ODM_AntDiv_Config(\r
- IN PDM_ODM_T pDM_Odm\r
+ IN PVOID pDM_VOID\r
)\r
{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;\r
#if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))\r
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("WIN Config Antenna Diversity\n"));\r
#elif (DM_ODM_SUPPORT_TYPE & (ODM_CE))\r
\r
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("CE Config Antenna Diversity\n"));\r
- //if(pDM_Odm->SupportICType & ODM_ANTDIV_SUPPORT)\r
- //{\r
- //pDM_Odm->SupportAbility |= ODM_BB_ANT_DIV;\r
- //}\r
+ if(pDM_Odm->SupportICType & ODM_ANTDIV_SUPPORT)\r
+ {\r
+ pDM_Odm->SupportAbility |= ODM_BB_ANT_DIV; \r
+ }\r
\r
if(pDM_Odm->SupportICType==ODM_RTL8723B)\r
{\r
pDM_Odm->AntDivType = S0S1_SW_ANTDIV;\r
- } \r
+ } \r
\r
#elif (DM_ODM_SUPPORT_TYPE & (ODM_AP))\r
\r
pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV; \r
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = CGCS_RX_HW_ANTDIV\n"));\r
panic_printk("[ 5G] : AntDiv Type = CGCS_RX_HW_ANTDIV\n");\r
- #elif( defined(CONFIG_5G_CG_TRX_DIVERSITY) )\r
+ #elif( defined(CONFIG_5G_CG_TRX_DIVERSITY)||defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A))\r
pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;\r
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = CG_TRX_HW_ANTDIV\n")); \r
panic_printk("[ 5G] : AntDiv Type = CG_TRX_HW_ANTDIV\n");\r
#if ( defined(CONFIG_2G_CGCS_RX_DIVERSITY) )\r
pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV;\r
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = CGCS_RX_HW_ANTDIV\n")); \r
- #elif( defined(CONFIG_2G_CG_TRX_DIVERSITY) )\r
+ #elif( defined(CONFIG_2G_CG_TRX_DIVERSITY) || defined(CONFIG_2G5G_CG_TRX_DIVERSITY_8881A))\r
pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;\r
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = CG_TRX_HW_ANTDIV\n"));\r
#elif( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) )\r
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Not Support 5G AntDivType\n"));\r
pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV);\r
}\r
- #endif \r
-#endif\r
+ #endif \r
+#endif \r
\r
ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SupportAbility = (( %x ))\n", pDM_Odm->SupportAbility ));\r
\r
\r
VOID\r
ODM_AntDivTimers(\r
- IN PDM_ODM_T pDM_Odm,\r
- IN u1Byte state\r
+ IN PVOID pDM_VOID, \r
+ IN u1Byte state\r
)\r
{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
if(state==INIT_ANTDIV_TIMMER)\r
{\r
#if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1)\r
ODM_InitializeTimer(pDM_Odm,&pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer_8723B,\r
(RT_TIMER_CALL_BACK)ODM_SW_AntDiv_Callback, NULL, "SwAntennaSwitchTimer_8723B");\r
- #elif (RTL8188E_SUPPORT == 1)\r
- #if (DM_ODM_SUPPORT_TYPE == ODM_AP)\r
+ #elif ( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) )\r
ODM_InitializeTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer,\r
(RT_TIMER_CALL_BACK)odm_FastAntTrainingCallback, NULL, "FastAntTrainingTimer");\r
- #endif\r
+ #endif\r
+\r
+ #ifdef ODM_EVM_ENHANCE_ANTDIV\r
+ ODM_InitializeTimer(pDM_Odm,&pDM_Odm->EVM_FastAntTrainingTimer,\r
+ (RT_TIMER_CALL_BACK)odm_EVM_FastAntTrainingCallback, NULL, "EVM_FastAntTrainingTimer");\r
#endif\r
}\r
else if(state==CANCEL_ANTDIV_TIMMER)\r
{\r
#if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1)\r
ODM_CancelTimer(pDM_Odm,&pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer_8723B);\r
- #elif (RTL8188E_SUPPORT == 1)\r
- #if (DM_ODM_SUPPORT_TYPE == ODM_AP)\r
+ #elif ( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) )\r
ODM_CancelTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer);\r
- #endif\r
+ #endif\r
+\r
+ #ifdef ODM_EVM_ENHANCE_ANTDIV\r
+ ODM_CancelTimer(pDM_Odm,&pDM_Odm->EVM_FastAntTrainingTimer);\r
#endif\r
}\r
else if(state==RELEASE_ANTDIV_TIMMER)\r
{\r
#if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1)\r
ODM_ReleaseTimer(pDM_Odm,&pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer_8723B);\r
- #elif (RTL8188E_SUPPORT == 1)\r
- #if (DM_ODM_SUPPORT_TYPE == ODM_AP)\r
+ #elif ( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) ) ||( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) )\r
ODM_ReleaseTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer);\r
- #endif\r
+ #endif\r
+\r
+ #ifdef ODM_EVM_ENHANCE_ANTDIV\r
+ ODM_ReleaseTimer(pDM_Odm,&pDM_Odm->EVM_FastAntTrainingTimer);\r
#endif\r
}\r
\r
\r
#endif //#if (defined(CONFIG_HW_ANTENNA_DIVERSITY))\r
\r
+VOID\r
+ODM_AntDivReset(\r
+ IN PVOID pDM_VOID\r
+ )\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ //2 [--8723B---]\r
+#if (RTL8723B_SUPPORT == 1)\r
+ if(pDM_Odm->SupportICType == ODM_RTL8723B)\r
+ {\r
+ #if(defined(CONFIG_HW_ANTENNA_DIVERSITY))\r
+ odm_S0S1_SWAntDiv_Reset_8723B(pDM_Odm);\r
+ #endif\r
+ }\r
+#endif\r
+}\r
+\r
+VOID\r
+odm_AntennaDiversityInit(\r
+ IN PVOID pDM_VOID\r
+ )\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ if(pDM_Odm->mp_mode == TRUE)\r
+ return;\r
+ \r
+ if(pDM_Odm->SupportICType & (ODM_OLD_IC_ANTDIV_SUPPORT))\r
+ {\r
+ #if (RTL8192C_SUPPORT==1) \r
+ #if (!(DM_ODM_SUPPORT_TYPE & (ODM_AP)))\r
+ ODM_OldIC_AntDiv_Init(pDM_Odm);\r
+ #endif\r
+ #endif\r
+ }\r
+ else\r
+ {\r
+ #if(defined(CONFIG_HW_ANTENNA_DIVERSITY))\r
+ ODM_AntDiv_Config(pDM_Odm);\r
+ ODM_AntDivInit(pDM_Odm);\r
+ #endif\r
+ }\r
+}\r
+\r
+VOID\r
+odm_AntennaDiversity(\r
+ IN PVOID pDM_VOID\r
+ )\r
+{\r
+ PDM_ODM_T pDM_Odm = (PDM_ODM_T)pDM_VOID;\r
+ if(pDM_Odm->mp_mode == TRUE)\r
+ return;\r
+\r
+ if(pDM_Odm->SupportICType & (ODM_OLD_IC_ANTDIV_SUPPORT))\r
+ {\r
+ #if (RTL8192C_SUPPORT==1)\r
+ #if (!(DM_ODM_SUPPORT_TYPE & (ODM_AP)))\r
+ ODM_OldIC_AntDiv(pDM_Odm);\r
+ #endif\r
+ #endif\r
+ }\r
+ else\r
+ {\r
+ #if(defined(CONFIG_HW_ANTENNA_DIVERSITY))\r
+ ODM_AntDiv(pDM_Odm);\r
+ #endif\r
+ }\r
+}\r
+\r
\r
projects / firefly-linux-kernel-4.4.55.git / blobdiff