8723BU: Update 8723BU wifi driver to version v4.3.16_14189.20150519_BTCOEX2015119...

[firefly-linux-kernel-4.4.55.git] / drivers / net / wireless / rockchip_wlan / rtl8723bu / hal / rtl8723b / rtl8723b_phycfg.c

diff --git a/drivers/net/wireless/rockchip_wlan/rtl8723bu/hal/rtl8723b/rtl8723b_phycfg.c b/drivers/net/wireless/rockchip_wlan/rtl8723bu/hal/rtl8723b/rtl8723b_phycfg.c
index 137270e00dad357586cc921d669312f19e4123de..d50f72435dcd9f4e6ee5c9ef9fdee6d5a16bf41e 100755 (executable)
--- a/drivers/net/wireless/rockchip_wlan/rtl8723bu/hal/rtl8723b/rtl8723b_phycfg.c
+++ b/drivers/net/wireless/rockchip_wlan/rtl8723bu/hal/rtl8723b/rtl8723b_phycfg.c
@@ -498,10 +498,6 @@ s32 PHY_MACConfig8723B(PADAPTER Adapter)
 #endif//CONFIG_EMBEDDED_FWIMG\r
        }\r
 \r
-#ifdef CONFIG_GPIO_WAKEUP\r
-       rtw_clear_hostwakeupgpio(Adapter);\r
-#endif // CONFIG_GPIO_WAKEUP\r
-\r
        return rtStatus;\r
 }\r
 \r
@@ -573,41 +569,41 @@ phy_ConfigBBWithMpHeaderFile(
        IN      u1Byte                  ConfigType)\r
 {\r
        int i;\r
-       u32*    Rtl8192CPHY_REGArray_Table_MP;\r
+       u32*    Rtl8723BPHY_REGArray_Table_MP;\r
        u16     PHY_REGArrayMPLen;\r
        HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);\r
 \r
 \r
        PHY_REGArrayMPLen = Rtl8723B_PHY_REG_Array_MPLength;\r
-       Rtl8192CPHY_REGArray_Table_MP = (u32*)Rtl8723B_PHY_REG_Array_MP;\r
+       Rtl8723BPHY_REGArray_Table_MP = (u32*)Rtl8723B_PHY_REG_Array_MP;\r
 \r
        if(ConfigType == BaseBand_Config_PHY_REG)\r
        {\r
                for(i=0;i<PHY_REGArrayMPLen;i=i+2)\r
                {\r
-                       if (Rtl8192CPHY_REGArray_Table_MP[i] == 0xfe) {\r
+                       if (Rtl8723BPHY_REGArray_Table_MP[i] == 0xfe) {\r
                                #ifdef CONFIG_LONG_DELAY_ISSUE\r
                                rtw_msleep_os(50);\r
                                #else\r
                                rtw_mdelay_os(50);\r
                                #endif\r
                        }\r
-                       else if (Rtl8192CPHY_REGArray_Table_MP[i] == 0xfd)\r
+                       else if (Rtl8723BPHY_REGArray_Table_MP[i] == 0xfd)\r
                                rtw_mdelay_os(5);\r
-                       else if (Rtl8192CPHY_REGArray_Table_MP[i] == 0xfc)\r
+                       else if (Rtl8723BPHY_REGArray_Table_MP[i] == 0xfc)\r
                                rtw_mdelay_os(1);\r
-                       else if (Rtl8192CPHY_REGArray_Table_MP[i] == 0xfb) {\r
+                       else if (Rtl8723BPHY_REGArray_Table_MP[i] == 0xfb) {\r
                                #ifdef CONFIG_LONG_DELAY_ISSUE\r
                                rtw_msleep_os(50);\r
                                #else\r
                                rtw_mdelay_os(50);\r
                                #endif\r
                        }\r
-                       else if (Rtl8192CPHY_REGArray_Table_MP[i] == 0xfa)\r
+                       else if (Rtl8723BPHY_REGArray_Table_MP[i] == 0xfa)\r
                                rtw_mdelay_os(5);\r
-                       else if (Rtl8192CPHY_REGArray_Table_MP[i] == 0xf9)\r
+                       else if (Rtl8723BPHY_REGArray_Table_MP[i] == 0xf9)\r
                                rtw_mdelay_os(1);\r
-                       PHY_SetBBReg(Adapter, Rtl8192CPHY_REGArray_Table_MP[i], bMaskDWord, Rtl8192CPHY_REGArray_Table_MP[i+1]);\r
+                       PHY_SetBBReg(Adapter, Rtl8723BPHY_REGArray_Table_MP[i], bMaskDWord, Rtl8723BPHY_REGArray_Table_MP[i+1]);\r
 \r
                        // Add 1us delay between BB/RF register setting.\r
                        rtw_mdelay_os(1);\r
@@ -625,28 +621,6 @@ phy_ConfigBBWithMpHeaderFile(
 \r
 #endif // #if (MP_DRIVER == 1)\r
 \r
-#if 0 //YJ,test,130321\r
-static VOID\r
-phy_BB8192C_Config_1T(\r
-       IN PADAPTER Adapter\r
-       )\r
-{\r
-       //for path - B\r
-       PHY_SetBBReg(Adapter, rFPGA0_TxInfo, 0x3, 0x2);\r
-       PHY_SetBBReg(Adapter, rFPGA1_TxInfo, 0x300033, 0x200022);\r
-\r
-       // 20100519 Joseph: Add for 1T2R config. Suggested by Kevin, Jenyu and Yunan.\r
-       PHY_SetBBReg(Adapter, rCCK0_AFESetting, bMaskByte3, 0x45);\r
-       PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, bMaskByte0, 0x23);\r
-       PHY_SetBBReg(Adapter, rOFDM0_AGCParameter1, 0x30, 0x1); // B path first AGC\r
-\r
-       PHY_SetBBReg(Adapter, 0xe74, 0x0c000000, 0x2);\r
-       PHY_SetBBReg(Adapter, 0xe78, 0x0c000000, 0x2);\r
-       PHY_SetBBReg(Adapter, 0xe7c, 0x0c000000, 0x2);\r
-       PHY_SetBBReg(Adapter, 0xe80, 0x0c000000, 0x2);\r
-       PHY_SetBBReg(Adapter, 0xe88, 0x0c000000, 0x2);\r
-}\r
-#endif\r
 \r
 static int\r
 phy_BB8723b_Config_ParaFile(\r
@@ -798,7 +772,7 @@ PHY_BBConfig8723B(
        RegVal = rtw_read16(Adapter, REG_SYS_FUNC_EN);\r
        rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal|BIT13|BIT0|BIT1));\r
 \r
-       // switch ant to BT\r
+       /* switch ant to BT */\r
 #ifdef CONFIG_USB_HCI\r
        rtw_write32(Adapter, 0x948, 0x0);       // USB use Antenna S0\r
 #else\r