intel-iommu: Tidy up iommu->gcmd handling

[firefly-linux-kernel-4.4.55.git] / drivers / pci / intel-iommu.c

diff --git a/drivers/pci/intel-iommu.c b/drivers/pci/intel-iommu.c
index 2e2c7406131d46144f0d37732d2daf1a31d39d89..bc99b1e47fbc4b869eeafcb3b175737d764b841a 100644 (file)
--- a/drivers/pci/intel-iommu.c
+++ b/drivers/pci/intel-iommu.c
@@ -819,7 +819,7 @@ static int iommu_alloc_root_entry(struct intel_iommu *iommu)
 static void iommu_set_root_entry(struct intel_iommu *iommu)
 {
        void *addr;
-       u32 cmd, sts;
+       u32 sts;
        unsigned long flag;
 
        addr = iommu->root_entry;
@@ -827,12 +827,11 @@ static void iommu_set_root_entry(struct intel_iommu *iommu)
        spin_lock_irqsave(&iommu->register_lock, flag);
        dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
 
-       cmd = iommu->gcmd | DMA_GCMD_SRTP;
-       writel(cmd, iommu->reg + DMAR_GCMD_REG);
+       writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
 
        /* Make sure hardware complete it */
        IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
-               readl, (sts & DMA_GSTS_RTPS), sts);
+                     readl, (sts & DMA_GSTS_RTPS), sts);
 
        spin_unlock_irqrestore(&iommu->register_lock, flag);
 }
@@ -844,12 +843,13 @@ static void iommu_flush_write_buffer(struct intel_iommu *iommu)
 
        if (!rwbf_quirk && !cap_rwbf(iommu->cap))
                return;
+
        spin_lock_irqsave(&iommu->register_lock, flag);
        writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
 
        /* Make sure hardware complete it */
        IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
-                       readl, (!(val & DMA_GSTS_WBFS)), val);
+                     readl, (!(val & DMA_GSTS_WBFS)), val);
 
        spin_unlock_irqrestore(&iommu->register_lock, flag);
 }
@@ -995,13 +995,13 @@ static int iommu_enable_translation(struct intel_iommu *iommu)
        unsigned long flags;
 
        spin_lock_irqsave(&iommu->register_lock, flags);
-       writel(iommu->gcmd|DMA_GCMD_TE, iommu->reg + DMAR_GCMD_REG);
+       iommu->gcmd |= DMA_GCMD_TE;
+       writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
 
        /* Make sure hardware complete it */
        IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
-               readl, (sts & DMA_GSTS_TES), sts);
+                     readl, (sts & DMA_GSTS_TES), sts);
 
-       iommu->gcmd |= DMA_GCMD_TE;
        spin_unlock_irqrestore(&iommu->register_lock, flags);
        return 0;
 }
@@ -1017,7 +1017,7 @@ static int iommu_disable_translation(struct intel_iommu *iommu)
 
        /* Make sure hardware complete it */
        IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
-               readl, (!(sts & DMA_GSTS_TES)), sts);
+                     readl, (!(sts & DMA_GSTS_TES)), sts);
 
        spin_unlock_irqrestore(&iommu->register_lock, flag);
        return 0;