return 0;
}
-static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc,
- unsigned long address)
+static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc, u32 reg)
{
struct sh_pfc_window *window;
+ phys_addr_t address = reg;
unsigned int i;
/* scan through physical windows and convert address */
return 1;
}
-unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
- unsigned long reg_width)
+u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
{
switch (reg_width) {
case 8:
return 0;
}
-void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,
- unsigned long data)
+void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
+ u32 data)
{
switch (reg_width) {
case 8:
static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
const struct pinmux_cfg_reg *crp,
- unsigned long in_pos,
- void __iomem **mapped_regp,
- unsigned long *maskp,
- unsigned long *posp)
+ unsigned int in_pos,
+ void __iomem **mapped_regp, u32 *maskp,
+ unsigned int *posp)
{
unsigned int k;
static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
const struct pinmux_cfg_reg *crp,
- unsigned long field, unsigned long value)
+ unsigned int field, u32 value)
{
void __iomem *mapped_reg;
- unsigned long mask, pos, data;
+ unsigned int pos;
+ u32 mask, data;
sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
- dev_dbg(pfc->dev, "write_reg addr = %lx, value = %ld, field = %ld, "
- "r_width = %ld, f_width = %ld\n",
+ dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
+ "r_width = %u, f_width = %u\n",
crp->reg, value, field, crp->reg_width, crp->field_width);
mask = ~(mask << pos);
}
static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
- const struct pinmux_cfg_reg **crp, int *fieldp,
- int *valuep)
+ const struct pinmux_cfg_reg **crp,
+ unsigned int *fieldp, u32 *valuep)
{
- const struct pinmux_cfg_reg *config_reg;
- unsigned long r_width, f_width, curr_width, ncomb;
- unsigned int k, m, n, pos, bit_pos;
+ unsigned int k = 0;
- k = 0;
while (1) {
- config_reg = pfc->info->cfg_regs + k;
-
- r_width = config_reg->reg_width;
- f_width = config_reg->field_width;
+ const struct pinmux_cfg_reg *config_reg =
+ pfc->info->cfg_regs + k;
+ unsigned int r_width = config_reg->reg_width;
+ unsigned int f_width = config_reg->field_width;
+ unsigned int curr_width;
+ unsigned int bit_pos;
+ unsigned int pos = 0;
+ unsigned int m = 0;
if (!r_width)
break;
- pos = 0;
- m = 0;
for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
+ u32 ncomb;
+ u32 n;
+
if (f_width)
curr_width = f_width;
else
int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
{
- const struct pinmux_cfg_reg *cr = NULL;
- u16 enum_id;
const struct pinmux_range *range;
- int in_range, pos, field, value;
- int ret;
+ int pos = 0;
switch (pinmux_type) {
case PINMUX_TYPE_GPIO:
return -EINVAL;
}
- pos = 0;
- enum_id = 0;
- field = 0;
- value = 0;
-
/* Iterate over all the configuration fields we need to update. */
while (1) {
+ const struct pinmux_cfg_reg *cr;
+ unsigned int field;
+ u16 enum_id;
+ u32 value;
+ int in_range;
+ int ret;
+
pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
if (pos < 0)
return pos;
}
static const struct platform_device_id sh_pfc_id_table[] = {
-#ifdef CONFIG_PINCTRL_PFC_EMEV2
- { "pfc-emev2", (kernel_ulong_t)&emev2_pinmux_info },
-#endif
#ifdef CONFIG_PINCTRL_PFC_R8A73A4
{ "pfc-r8a73a4", (kernel_ulong_t)&r8a73a4_pinmux_info },
#endif
#ifdef CONFIG_PINCTRL_PFC_R8A7779
{ "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info },
#endif
-#ifdef CONFIG_PINCTRL_PFC_R8A7790
- { "pfc-r8a7790", (kernel_ulong_t)&r8a7790_pinmux_info },
-#endif
-#ifdef CONFIG_PINCTRL_PFC_R8A7791
- { "pfc-r8a7791", (kernel_ulong_t)&r8a7791_pinmux_info },
-#endif
#ifdef CONFIG_PINCTRL_PFC_SH7203
{ "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
#endif