Merge branch 'iov_iter' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs

[firefly-linux-kernel-4.4.55.git] / drivers / scsi / csiostor / csio_hw_chip.h

diff --git a/drivers/scsi/csiostor/csio_hw_chip.h b/drivers/scsi/csiostor/csio_hw_chip.h
index 4752fed476dfb293e04d5860e1fad2f6116f9327..b56a11d817be32318976b15111dfcee8b9e58bcb 100644 (file)
--- a/drivers/scsi/csiostor/csio_hw_chip.h
+++ b/drivers/scsi/csiostor/csio_hw_chip.h
@@ -37,24 +37,27 @@
 #include "csio_defs.h"
 
 /* Define MACRO values */
-#define CSIO_HW_T4                             0x4000
-#define CSIO_T4_FCOE_ASIC                      0x4600
 #define CSIO_HW_T5                             0x5000
 #define CSIO_T5_FCOE_ASIC                      0x5600
 #define CSIO_HW_CHIP_MASK                      0xF000
 
-#define T4_REGMAP_SIZE                         (160 * 1024)
 #define T5_REGMAP_SIZE                         (332 * 1024)
-#define FW_FNAME_T4                            "cxgb4/t4fw.bin"
 #define FW_FNAME_T5                            "cxgb4/t5fw.bin"
-#define FW_CFG_NAME_T4                         "cxgb4/t4-config.txt"
 #define FW_CFG_NAME_T5                         "cxgb4/t5-config.txt"
 
-/* Define static functions */
-static inline int csio_is_t4(uint16_t chip)
-{
-       return (chip == CSIO_HW_T4);
-}
+#define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
+#define CHELSIO_CHIP_FPGA          0x100
+#define CHELSIO_CHIP_VERSION(code) (((code) >> 12) & 0xf)
+#define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
+
+#define CHELSIO_T5             0x5
+
+enum chip_type {
+       T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
+       T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
+       T5_FIRST_REV    = T5_A0,
+       T5_LAST_REV     = T5_A1,
+};
 
 static inline int csio_is_t5(uint16_t chip)
 {
@@ -65,30 +68,22 @@ static inline int csio_is_t5(uint16_t chip)
 #define CSIO_DEVICE(devid, idx)                                                \
        { PCI_VENDOR_ID_CHELSIO, (devid), PCI_ANY_ID, PCI_ANY_ID, 0, 0, (idx) }
 
-#define CSIO_HW_PIDX(hw, index)                                                \
-       (csio_is_t4(hw->chip_id) ? (PIDX(index)) :                      \
-                                       (PIDX_T5(index) | DBTYPE(1U)))
-
-#define CSIO_HW_LP_INT_THRESH(hw, val)                                 \
-       (csio_is_t4(hw->chip_id) ? (LP_INT_THRESH(val)) :               \
-                                       (V_LP_INT_THRESH_T5(val)))
-
-#define CSIO_HW_M_LP_INT_THRESH(hw)                                    \
-       (csio_is_t4(hw->chip_id) ? (LP_INT_THRESH_MASK) : (M_LP_INT_THRESH_T5))
-
-#define CSIO_MAC_INT_CAUSE_REG(hw, port)                               \
-       (csio_is_t4(hw->chip_id) ? (PORT_REG(port, XGMAC_PORT_INT_CAUSE)) : \
-                               (T5_PORT_REG(port, MAC_PORT_INT_CAUSE)))
-
-#define FW_VERSION_MAJOR(hw) (csio_is_t4(hw->chip_id) ? 1 : 0)
-#define FW_VERSION_MINOR(hw) (csio_is_t4(hw->chip_id) ? 2 : 0)
-#define FW_VERSION_MICRO(hw) (csio_is_t4(hw->chip_id) ? 8 : 0)
-
-#define CSIO_FW_FNAME(hw)                                              \
-       (csio_is_t4(hw->chip_id) ? FW_FNAME_T4 : FW_FNAME_T5)
-
-#define CSIO_CF_FNAME(hw)                                              \
-       (csio_is_t4(hw->chip_id) ? FW_CFG_NAME_T4 : FW_CFG_NAME_T5)
+#include "t4fw_api.h"
+#include "t4fw_version.h"
+
+#define FW_VERSION(chip) ( \
+               FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
+               FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
+               FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
+               FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
+#define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
+
+struct fw_info {
+       u8 chip;
+       char *fs_name;
+       char *fw_mod_name;
+       struct fw_hdr fw_hdr;
+};
 
 /* Declare ENUMS */
 enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 };
@@ -96,7 +91,6 @@ enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 };
 enum {
        MEMWIN_APERTURE = 2048,
        MEMWIN_BASE     = 0x1b800,
-       MEMWIN_CSIOSTOR = 6,            /* PCI-e Memory Window access */
 };
 
 /* Slow path handlers */
@@ -122,7 +116,6 @@ struct csio_hw_chip_ops {
        void (*chip_dfs_create_ext_mem)(struct csio_hw *);
 };
 
-extern struct csio_hw_chip_ops t4_ops;
 extern struct csio_hw_chip_ops t5_ops;
 
 #endif /* #ifndef __CSIO_HW_CHIP_H__ */